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AxC1271/README.md

Hi, I'm Andrew!

πŸ’» Computer Engineer Documenting my Projects/Learning
βš™οΈ Studying Computer Architecture and RTL Design
πŸ“Ÿ Skilled in Verilog/SystemVerilog and FPGA toolchains
πŸ§‘β€πŸŽ“ Carnegie Mellon University MS ECE Student

Fun Facts about Me:

My interests are coding, badminton, rock climbing, and baking! Outside of academics, you can catch me skateboarding around campus, playing chess, doodling, or sleeping. :)

πŸ’» Tech Stack:

RISC-V SystemVerilog VHDL C Python PlatformIO Raspberry Pi Intel AMD nVIDIA Linux Arm Xilinx CMake Bash

πŸš€ Project Highlights:

πŸ”¬ RISC-V SoC v2

5-stage pipelined RISC-V processor with split L1 caches (direct-mapped I-cache, 2-way set-associative D-cache). Built from scratch and validated in SystemVerilog.

View Repo β†’

πŸŽ“ CWRU CPU β€” Hacker Fab

Architecting and leading an underclassmen design team to implement a single-cycle RISC-V processor in Verilog and tape it out via Tiny Tapeout, targeting June 2026 submission.

View Repo β†’

πŸ•ΉοΈ Tiny Pong β€” SkyWater 130nm Tapeout

A Pong VGA controller taped out on SkyWater 130nm process via Tiny Tapeout. My first custom silicon tapeout project publicly available on GitHub.

View Repo β†’

⚑ PCB Design & Magic VLSI

Explored physical design through PCB layout and Magic VLSI β€” bridging the gap between RTL and silicon through hands-on tooling at the transistor level.

πŸ“Š GitHub Stats:

Pinned Loading

  1. RISCV-v2 RISCV-v2 Public

    This SoC contains a more complex pipelined processor that builds on a previous RISC-V CPU GitHub repository in SystemVerilog, but adds an external bootloader for serial programming via UART, proper…

    SystemVerilog 1

  2. Verilyzer Verilyzer Public

    This is a fun and self-learning project exploring compiler design using Bison/Flex to compile and simulate Verilog circuits in C/C++.

    C 1

  3. TinyPong TinyPong Public

    This is a TinyTapeout submission (TT-Sky25b) of a simple single-player Pong game written in Verilog as an addition to my original VGA Pong project. The final project is then fabbed onto a physical …

    Verilog 1

  4. RISCV-v1 RISCV-v1 Public

    This is a RTL approach to implementing a simple RISC-V processor using VHDL and the Basys3 FPGA board. Fully synthesizable with instructions to run a simple Fibonacci sequence.

    VHDL 1

  5. STM32-DevBoard STM32-DevBoard Public

    This is my personal project on using KiCad 7.0 to design, build, and manufacture a simple STM32 development board. Later, the board will be interfaced with a UART receiver on my FPGA board.

    VHDL