Single-port ROM wrapper.
| No. | File name | Description |
|---|---|---|
| 1 | README.md | Module Specification |
| 2 | FIREEEE_ROM.v | Module |
| 3 | FIREEEE_ROM_tb.sv | Testbench |
| 4 | Sim | Simulation Scripts |
| Item | Status |
|---|---|
| Version | 0.01 |
| Date | 2026/03/17 |
| Verified | Yes |
| Real Machine Checked | No |
- RTL simulation
- Code coverage
Some inputs may not take effect depending on the ROM used in combination with this module.
| Port name | Description | Synchronous / Asynchronous | Clock Domain | Active low |
|---|---|---|---|---|
| CLK_I | Clock | - | - | No |
| RADDR_I | Write Address | Synchronous | CLK_I | No |
| Port name | Description | Synchronous / Asynchronous | Clock Domain | Active low |
|---|---|---|---|---|
| RDATA_O | Read Data | Synchronous | CLK_I | No |
Some parameters may not take effect depending on the ROM used in combination with this module.
| Parameter name | Description | Default Value |
|---|---|---|
| DATA_WIDTH | Data Bit Width | 8 |
| ADDR_WIDTH | Address Width | 8 |
| OUT_REG_EN | Output Register Enable | 1'b0 (Disable) |
| ROM_INIT_FILE | ROM Initialization File Name | "initrom.hex" |
No timing chart in this module. Please see FIREEEE_COEF_ROM for actual operation.
- Some inputs and parametes may not take effect depending on the ROM used in combination with this module.
- You have to your own single clock simple dual-port RAM by define macro.
Initial Release of the Specification.
- Add module & related files. (2026/03/17)
- Add simulation & verification results. (2026/03/17)