Fix I->regs.read and I->regs.write bug.

GJDuck · GJDuck · commit dba5b7ab51b5 · 2021-07-14T16:17:19.000+08:00
Some registers were not added as expected.
diff --git a/src/e9tool/e9x86_64.cpp b/src/e9tool/e9x86_64.cpp
@@ -235,18 +235,25 @@ void e9frontend::getInstrInfo(const ELF *elf, const Instr *I, InstrInfo *info,
             switch (D->operands[i].type)
             {
                 case ZYDIS_OPERAND_TYPE_REGISTER:
-                    if (read)
-                        info->regs.read[k++] = convert(D->operands[i].reg.value);
-                    if (write)
-                        info->regs.write[l++] = convert(D->operands[i].reg.value);
+                {
+                    Register r = convert(D->operands[i].reg.value);
+                    if (read && r != REGISTER_INVALID)
+                        info->regs.read[k++] = r;
+                    if (write && r != REGISTER_INVALID)
+                        info->regs.write[l++] = r;
                     break;
+                }
                 case ZYDIS_OPERAND_TYPE_MEMORY:
+                {
                     info->regs.read[k++] = seg;
-                    if (D->operands[i].mem.base != ZYDIS_REGISTER_NONE)
-                        info->regs.read[k++] = convert(D->operands[i].mem.base);
-                    if (D->operands[i].mem.index != ZYDIS_REGISTER_NONE)
-                        info->regs.read[k++] = convert(D->operands[i].mem.index);
+                    Register r = convert(D->operands[i].mem.base);
+                    if (r != REGISTER_INVALID)
+                        info->regs.read[k++] = r;
+                    r = convert(D->operands[i].mem.index);
+                    if (r != REGISTER_INVALID)
+                        info->regs.read[k++] = r;
                     break;
+                }
                 default:
                     break;
             }
diff --git a/test/regtest/write_bug.exp b/test/regtest/write_bug.exp
@@ -0,0 +1,2 @@
+0000000083838383:0000000000000006:0000000000000006: 49 83 c1 06             add $0x6, %r9
+PASSED
diff --git a/test/regtest/write_bug.in b/test/regtest/write_bug.in
@@ -0,0 +1 @@
+./test -M 'imm[0] == 0x6 && %r9 in writes' -A 'call entry(r9,imm[0],0x6,instr,size,asm)@inst'

Original file line number	Diff line number	Diff line change
`@@ -0,0 +1,2 @@`
	`1`	`+0000000083838383:0000000000000006:0000000000000006: 49 83 c1 06 add $0x6, %r9`
	`2`	`+PASSED`
Original file line number	Diff line number	Diff line change
`@@ -0,0 +1 @@`
	`1`	`+./test -M 'imm[0] == 0x6 && %r9 in writes' -A 'call entry(r9,imm[0],0x6,instr,size,asm)@inst'`