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Start RCC update to use ClockHelper v2.0 data (ZigEmbeddedGroup#744)
1 parent 05d91de commit 157b58f

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19 files changed

+359
-2611
lines changed

19 files changed

+359
-2611
lines changed

‎examples/stmicro/stm32/src/stm32f1xx/advanced_adc.zig‎

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -48,7 +48,12 @@ fn adc_to_temp(val: usize) f32 {
4848
}
4949

5050
pub fn main() !void {
51-
try rcc.apply_clock(.{ .ADCprescaler = .RCC_ADCPCLK2_DIV2 });
51+
_ = try rcc.apply(.{
52+
.ADCPresc = .RCC_ADCPCLK2_DIV2,
53+
.flags = .{
54+
.USE_ADC1 = true,
55+
},
56+
});
5257

5358
rcc.enable_clock(.DMA1);
5459
rcc.enable_clock(.TIM2);

‎examples/stmicro/stm32/src/stm32f1xx/gpio.zig‎

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -7,12 +7,16 @@ const gpio = stm32.gpio;
77
const time = stm32.time;
88

99
pub fn main() !void {
10-
try rcc.apply_clock(.{
11-
.SysClkSource = .RCC_SYSCLKSOURCE_PLLCLK,
10+
_ = try rcc.apply(.{
11+
.SYSCLKSource = .RCC_SYSCLKSOURCE_PLLCLK,
1212
.PLLSource = .RCC_PLLSOURCE_HSE,
1313
.PLLMUL = .RCC_PLL_MUL9,
14-
.APB1Prescaler = .RCC_HCLK_DIV2,
15-
.RTCClkSource = .RCC_RTCCLKSOURCE_LSI,
14+
.APB1CLKDivider = .RCC_HCLK_DIV2,
15+
.RTCClockSelection = .RCC_RTCCLKSOURCE_LSI,
16+
.flags = .{
17+
.RTCUsed_ForRCC = true,
18+
.HSEOscillator = true,
19+
},
1620
});
1721
rcc.enable_clock(.GPIOC);
1822

‎examples/stmicro/stm32/src/stm32f1xx/rcc.zig‎

Lines changed: 10 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -16,15 +16,20 @@ pub const microzig_options = microzig.Options{
1616

1717
const clk_config = rcc.Config{
1818
.PLLSource = .RCC_PLLSOURCE_HSE,
19-
.HSEDivPLL = .RCC_HSE_PREDIV_DIV2,
19+
.HSEDivPLL = .RCC_HSE_PREDIV_DIV1,
2020
.PLLMUL = .RCC_PLL_MUL2,
21-
.SysClkSource = .RCC_SYSCLKSOURCE_PLLCLK,
22-
.APB1Prescaler = .RCC_HCLK_DIV1,
23-
.MCOMult = .RCC_MCO1SOURCE_SYSCLK,
21+
.SYSCLKSource = .RCC_SYSCLKSOURCE_PLLCLK,
22+
.APB1CLKDivider = .RCC_HCLK_DIV2,
23+
.RCC_MCOSource = .RCC_MCO1SOURCE_SYSCLK,
24+
.flags = .{
25+
.HSEOscillator = true,
26+
.MCOUsed_ForRCC = true,
27+
.MCOConfig = true,
28+
},
2429
};
2530

2631
pub fn main() !void {
27-
try rcc.apply_clock(clk_config);
32+
_ = try rcc.apply(clk_config);
2833
rcc.enable_clock(.GPIOA);
2934
rcc.enable_clock(.AFIO);
3035
rcc.enable_clock(.USART1);

‎examples/stmicro/stm32/src/stm32f1xx/rtc.zig‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,10 @@ pub fn main() !void {
3030
//by the system reset, so we need to check if it is already running.
3131
//If it is not running, we will configure it and enable it.
3232
if (fresh_start()) {
33-
try rcc.apply_clock(.{ .RTCClkSource = .RCC_RTCCLKSOURCE_LSE });
33+
_ = try rcc.apply(.{
34+
.RTCClockSelection = .RCC_RTCCLKSOURCE_LSE,
35+
.flags = .{ .RTCUsed_ForRCC = true, .LSEOscillator = true },
36+
});
3437
rcc.enable_clock(.PWR);
3538
rcc.enable_clock(.BKP);
3639

@@ -66,9 +69,10 @@ pub fn main() !void {
6669
}
6770

6871
fn fresh_start() bool {
72+
const power_down: bool = hal.Reset_Reason == .POR_or_PDR;
6973
rcc.enable_clock(.PWR);
7074
rcc.enable_clock(.BKP);
7175
const data: u32 = (@as(u32, bkp.BackupData1[1].data) << 16) | bkp.BackupData1[0].data;
7276
rcc.disable_all_clocks();
73-
return data != 0xDEADBEEF;
77+
return (data != 0xDEADBEEF) or power_down;
7478
}

‎examples/stmicro/stm32/src/stm32f1xx/timer.zig‎

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,10 @@ const gpio = stm32.gpio;
1010
const GPTimer = stm32.timer.GPTimer;
1111
const time = stm32.time;
1212

13+
//pub const microzig_options: microzig.Options = .{
14+
// .interrupts = .{ .TIM3 = .{ .c = time.TIM_handler } },
15+
//};
16+
1317
//gpios
1418
const ch1 = gpio.Pin.from_port(.A, 0);
1519
const ch2 = gpio.Pin.from_port(.A, 1);
@@ -23,7 +27,10 @@ pub fn main() !void {
2327
//first we need to enable the clocks for the GPIO and TIM peripherals
2428

2529
//use HSE as system clock source, more stable than HSI
26-
try rcc.apply_clock(.{ .SysClkSource = .RCC_SYSCLKSOURCE_HSE });
30+
_ = try rcc.apply(.{
31+
.SYSCLKSource = .RCC_SYSCLKSOURCE_HSE,
32+
.flags = .{ .HSEOscillator = true },
33+
});
2734

2835
//enable GPIOA and TIM2, TIM3, AFIO clocks
2936
//AFIO is needed for alternate function remapping, not used in this example but eneble for easy remapping

‎examples/stmicro/stm32/src/stm32f1xx/timer_capture.zig‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -65,7 +65,10 @@ pub fn main() !void {
6565
//first we need to enable the clocks for the GPIO and TIM peripherals
6666

6767
//use HSE as system clock source, more stable than HSI
68-
try rcc.apply_clock(.{ .SysClkSource = .RCC_SYSCLKSOURCE_HSE });
68+
_ = try rcc.apply(.{
69+
.SYSCLKSource = .RCC_SYSCLKSOURCE_HSE,
70+
.flags = .{ .HSEOscillator = true },
71+
});
6972

7073
//enable GPIOA and TIM2, TIM3, AFIO clocks
7174
//AFIO is needed for alternate function remapping, not used in this example but eneble for easy remapping

‎examples/stmicro/stm32/src/stm32f1xx/usb_cdc.zig‎

Lines changed: 7 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -412,12 +412,16 @@ fn CDC_read(buf: []u8, timeout: ?Duration) ![]const u8 {
412412
}
413413

414414
pub fn main() !void {
415-
try rcc.apply_clock(.{
415+
_ = try rcc.apply(.{
416416
.PLLSource = .RCC_PLLSOURCE_HSE,
417417
.PLLMUL = .RCC_PLL_MUL9,
418-
.SysClkSource = .RCC_SYSCLKSOURCE_PLLCLK,
419-
.APB1Prescaler = .RCC_HCLK_DIV2,
418+
.SYSCLKSource = .RCC_SYSCLKSOURCE_PLLCLK,
419+
.APB1CLKDivider = .RCC_HCLK_DIV2,
420420
.USBPrescaler = .RCC_USBCLKSOURCE_PLL_DIV1_5,
421+
.flags = .{
422+
.HSEOscillator = true,
423+
.USBUsed_ForRCC = true,
424+
},
421425
});
422426

423427
rcc.enable_clock(.GPIOA);

‎examples/stmicro/stm32/src/stm32f1xx/usb_hid.zig‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -256,12 +256,13 @@ fn report(keys: []const u8) void {
256256
}
257257

258258
pub fn main() !void {
259-
try rcc.apply_clock(.{
259+
_ = try rcc.apply(.{
260260
.PLLSource = .RCC_PLLSOURCE_HSE,
261261
.PLLMUL = .RCC_PLL_MUL9,
262-
.SysClkSource = .RCC_SYSCLKSOURCE_PLLCLK,
263-
.APB1Prescaler = .RCC_HCLK_DIV2,
262+
.SYSCLKSource = .RCC_SYSCLKSOURCE_PLLCLK,
263+
.APB1CLKDivider = .RCC_HCLK_DIV2,
264264
.USBPrescaler = .RCC_USBCLKSOURCE_PLL_DIV1_5,
265+
.flags = .{ .HSEOscillator = true, .USBUsed_ForRCC = true },
265266
});
266267

267268
rcc.enable_clock(.GPIOA);

‎port/stmicro/stm32/build.zig‎

Lines changed: 11 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,17 @@ boards: struct {
1515

1616
pub fn init(dep: *std.Build.Dependency) Self {
1717
const b = dep.builder;
18-
const chips = Chips.init(dep);
18+
19+
const clockhelper_dep = b.dependency("ClockHelper", .{}).module("clockhelper");
20+
21+
const hal_imports: []std.Build.Module.Import = b.allocator.dupe(std.Build.Module.Import, &.{
22+
.{
23+
.name = "ClockTree",
24+
.module = clockhelper_dep,
25+
},
26+
}) catch @panic("out of memory");
27+
28+
const chips = Chips.init(dep, hal_imports);
1929

2030
return .{
2131
.chips = chips,

‎port/stmicro/stm32/build.zig.zon‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,10 @@
99
.url = "git+https://github.com/embassy-rs/stm32-data-generated.git#5198a6e36b24f6d79c4ac91af5e61e8d54667d88",
1010
.hash = "N-V-__8AAFi8WBlOh-NikHFVBjzQE0F1KixgKjVWYnlijPNm",
1111
},
12+
.ClockHelper = .{
13+
.url = "git+https://github.com/ZigEmbeddedGroup/ClockHelper#7fd073b1be9544941c15f9a63032ed06149ddb70",
14+
.hash = "ClockHelper-2.0.0-RcMaOSniGQHXH_qeoZbQDG64XThqpXTVPMfJ6P7LHpYY",
15+
},
1216
},
1317
.paths = .{
1418
"README.md",

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