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RISCV32 common module (ZigEmbeddedGroup#503)
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24 files changed

Lines changed: 1009 additions & 1372 deletions

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‎.github/workflows/ci.yml‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -75,7 +75,7 @@ jobs:
7575
version: ${{ env.ZIG_VERSION }}
7676
- name: Unit Test ESP Image
7777
run: zig build test
78-
working-directory: tools/esp_image
78+
working-directory: tools/esp-image
7979

8080
stm32-gen-check:
8181
name: Check that stm32 generated code is up to date

‎build-internals/build.zig‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@ const regz = @import("regz");
77
pub const Patch = regz.patch.Patch;
88
const uf2 = @import("uf2");
99
pub const FamilyId = uf2.FamilyId;
10-
const esp_image = @import("esp_image");
10+
const esp_image = @import("esp-image");
1111

1212
pub fn build(b: *Build) void {
1313
_ = b.addModule("build-internals", .{

‎build-internals/build.zig.zon‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
.dependencies = .{
66
.regz = .{ .path = "../tools/regz" },
77
.uf2 = .{ .path = "../tools/uf2" },
8-
.esp_image = .{ .path = "../tools/esp_image" },
8+
.@"esp-image" = .{ .path = "../tools/esp-image" },
99
},
1010
.paths = .{
1111
"build.zig",

‎build.zig‎

Lines changed: 33 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -114,7 +114,7 @@ fn generate_release_steps(b: *Build) void {
114114
for (exe_targets) |t| {
115115
const release_target = b.resolveTargetQuery(t);
116116

117-
const esp_image_dep = b.dependency("tools/esp_image", .{
117+
const esp_image_dep = b.dependency("tools/esp-image", .{
118118
.optimize = .ReleaseSafe,
119119
.target = release_target,
120120
});
@@ -378,7 +378,7 @@ pub fn MicroBuild(port_select: PortSelect) type {
378378

379379
const zig_resolved_target = b.resolveTargetQuery(options.zig_target orelse target.zig_target);
380380

381-
const cpu = options.cpu orelse target.cpu orelse get_default_cpu(zig_resolved_target.result, mb.core_dep);
381+
const cpu = options.cpu orelse target.cpu orelse mb.get_default_cpu(zig_resolved_target.result);
382382
const maybe_hal = options.hal orelse target.hal;
383383
const maybe_board = options.board orelse target.board;
384384

@@ -662,8 +662,8 @@ pub fn MicroBuild(port_select: PortSelect) type {
662662

663663
.dfu => @panic("DFU is not implemented yet. See https://github.com/ZigEmbeddedGroup/microzig/issues/145 for more details!"),
664664

665-
.esp => |options| @import("tools/esp_image").from_elf(
666-
fw.mb.dep.builder.dependency("tools/esp_image", .{}),
665+
.esp => |options| @import("tools/esp-image").from_elf(
666+
fw.mb.dep.builder.dependency("tools/esp-image", .{}),
667667
elf_file,
668668
options,
669669
),
@@ -738,31 +738,37 @@ pub fn MicroBuild(port_select: PortSelect) type {
738738
fw.artifact.addObjectFile(source);
739739
}
740740
};
741-
};
742-
}
743741

744-
fn get_default_cpu(target: std.Target, core_dep: *Build.Dependency) Cpu {
745-
if (std.mem.eql(u8, target.cpu.model.name, "avr5")) {
746-
return .{
747-
.name = "avr5",
748-
.root_source_file = core_dep.namedLazyPath("cpu_avr5"),
749-
};
750-
} else if (std.mem.startsWith(u8, target.cpu.model.name, "cortex_m")) {
751-
return .{
752-
.name = target.cpu.model.name,
753-
.root_source_file = core_dep.namedLazyPath("cpu_cortex_m"),
754-
};
755-
} else if (target.cpu.arch.isRISCV() and target.ptrBitWidth() == 32) {
756-
return .{
757-
.name = "riscv32",
758-
.root_source_file = core_dep.namedLazyPath("cpu_riscv32"),
759-
};
760-
}
742+
fn get_default_cpu(mb: *Self, target: std.Target) Cpu {
743+
if (std.mem.eql(u8, target.cpu.model.name, "avr5")) {
744+
return .{
745+
.name = "avr5",
746+
.root_source_file = mb.core_dep.namedLazyPath("cpu_avr5"),
747+
};
748+
} else if (std.mem.startsWith(u8, target.cpu.model.name, "cortex_m")) {
749+
return .{
750+
.name = target.cpu.model.name,
751+
.root_source_file = mb.core_dep.namedLazyPath("cpu_cortex_m"),
752+
};
753+
} else if (target.cpu.arch.isRISCV() and target.ptrBitWidth() == 32) {
754+
return .{
755+
.name = "riscv32",
756+
.root_source_file = mb.core_dep.namedLazyPath("cpu_riscv32"),
757+
.imports = mb.builder.allocator.dupe(Build.Module.Import, &.{
758+
.{
759+
.name = "riscv32-common",
760+
.module = mb.dep.builder.dependency("modules/riscv32-common", .{}).module("riscv32-common"),
761+
},
762+
}) catch @panic("OOM"),
763+
};
764+
}
761765

762-
std.debug.panic(
763-
"No default cpu configuration for `{s}`. Please specify a cpu either in the target or in the options for creating the firmware.",
764-
.{target.cpu.model.name},
765-
);
766+
std.debug.panic(
767+
"No default cpu configuration for `{s}`. Please specify a cpu either in the target or in the options for creating the firmware.",
768+
.{target.cpu.model.name},
769+
);
770+
}
771+
};
766772
}
767773

768774
pub inline fn custom_lazy_import(

‎build.zig.zon‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,10 +12,11 @@
1212
// tools
1313
.@"tools/regz" = .{ .path = "tools/regz" },
1414
.@"tools/uf2" = .{ .path = "tools/uf2" },
15-
.@"tools/esp_image" = .{ .path = "tools/esp_image" },
15+
.@"tools/esp-image" = .{ .path = "tools/esp-image" },
1616

1717
// modules
1818
.@"modules/foundation-libc" = .{ .path = "modules/foundation-libc" },
19+
.@"modules/riscv32-common" = .{ .path = "modules/riscv32-common" },
1920

2021
// simulators
2122
.@"sim/aviron" = .{ .path = "sim/aviron", .lazy = true },

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