ch32v: Improve clock configuration (ZigEmbeddedGroup#767)

Grazfather · web-flow · commit cec680031e28 · 2025-12-15T16:42:56.000-08:00
diff --git a/port/wch/ch32v/src/boards/CH32V003F4P6-R0-1v1.zig b/port/wch/ch32v/src/boards/CH32V003F4P6-R0-1v1.zig
@@ -1,5 +1,15 @@
 // CH32V003F4P6_MINI
 // CH32V003
 pub const chip = @import("chip");
+pub const microzig = @import("microzig");
+const ch32v = microzig.hal;
 
-pub const cpu_frequency = 24_000_000; // 24 MHz
+/// Clock configuration for this board
+/// CH32V003 runs at 24 MHz when using HSI with PLL
+pub const clock_config: ch32v.clocks.Config = .{
+    .source = .hsi,
+    .target_frequency = 24_000_000,
+};
+
+/// CPU frequency is derived from clock config
+pub const cpu_frequency = clock_config.target_frequency;
diff --git a/port/wch/ch32v/src/boards/CH32V103-R1-1v1.zig b/port/wch/ch32v/src/boards/CH32V103-R1-1v1.zig
@@ -4,10 +4,17 @@ pub const chip = @import("chip");
 pub const microzig = @import("microzig");
 const ch32v = microzig.hal;
 
-pub const cpu_frequency = 48_000_000; // 48 MHz
+/// Clock configuration for this board
+pub const clock_config: ch32v.clocks.Config = .{
+    .source = .hsi,
+    .target_frequency = 48_000_000,
+};
+
+/// CPU frequency is derived from clock config
+pub const cpu_frequency = clock_config.target_frequency;
 
 /// Board-specific init: set 48 MHz clock, enable SysTick time
 pub fn init() void {
-    ch32v.clocks.init_48mhz_hsi();
+    ch32v.clocks.init(clock_config);
     ch32v.time.init();
 }
diff --git a/port/wch/ch32v/src/boards/CH32V307V-R1-1v0.zig b/port/wch/ch32v/src/boards/CH32V307V-R1-1v0.zig
@@ -4,10 +4,17 @@ pub const microzig = @import("microzig");
 pub const chip = @import("chip");
 const ch32v = microzig.hal;
 
-pub const cpu_frequency = 48_000_000; // 48 MHz
+/// Clock configuration for this board
+pub const clock_config: ch32v.clocks.Config = .{
+    .source = .hsi,
+    .target_frequency = 48_000_000,
+};
+
+/// CPU frequency is derived from clock config
+pub const cpu_frequency = clock_config.target_frequency;
 
 /// Board-specific init: set 48 MHz clock, enable SysTick time
 pub fn init() void {
-    ch32v.clocks.init_48mhz_hsi();
+    ch32v.clocks.init(clock_config);
     ch32v.time.init();
 }
diff --git a/port/wch/ch32v/src/boards/CH32Vx03C-R0-1v0.zig b/port/wch/ch32v/src/boards/CH32Vx03C-R0-1v0.zig
@@ -4,10 +4,17 @@ pub const microzig = @import("microzig");
 pub const chip = @import("chip");
 const ch32v = microzig.hal;
 
-pub const cpu_frequency = 48_000_000; // 48 MHz
+/// Clock configuration for this board
+pub const clock_config: ch32v.clocks.Config = .{
+    .source = .hsi,
+    .target_frequency = 48_000_000,
+};
+
+/// CPU frequency is derived from clock config
+pub const cpu_frequency = clock_config.target_frequency;
 
 /// Board-specific init: set 48 MHz clock, enable SysTick time
 pub fn init() void {
-    ch32v.clocks.init_48mhz_hsi();
+    ch32v.clocks.init(clock_config);
     ch32v.time.init();
 }
diff --git a/port/wch/ch32v/src/boards/LANA_TNY.zig b/port/wch/ch32v/src/boards/LANA_TNY.zig
@@ -5,11 +5,18 @@ pub const microzig = @import("microzig");
 pub const chip = @import("chip");
 const ch32v = microzig.hal;
 
-pub const cpu_frequency = 48_000_000; // 48 MHz
+/// Clock configuration for this board
+pub const clock_config: ch32v.clocks.Config = .{
+    .source = .hsi,
+    .target_frequency = 48_000_000,
+};
+
+/// CPU frequency is derived from clock config
+pub const cpu_frequency = clock_config.target_frequency;
 
 /// Board-specific init: set 48 MHz clock, enable SysTick time
 pub fn init() void {
-    ch32v.clocks.init_48mhz_hsi();
+    ch32v.clocks.init(clock_config);
     ch32v.time.init();
 }
 
diff --git a/port/wch/ch32v/src/boards/Suzuduino_Uno_V1b.zig b/port/wch/ch32v/src/boards/Suzuduino_Uno_V1b.zig
@@ -5,7 +5,14 @@ pub const microzig = @import("microzig");
 pub const chip = @import("chip");
 const ch32v = microzig.hal;
 
-pub const cpu_frequency = 48_000_000; // 48 MHz
+/// Clock configuration for this board
+pub const clock_config: ch32v.clocks.Config = .{
+    .source = .hsi,
+    .target_frequency = 48_000_000,
+};
+
+/// CPU frequency is derived from clock config
+pub const cpu_frequency = clock_config.target_frequency;
 
 pub const pin_config = ch32v.pins.GlobalConfiguration{
     .GPIOA = .{
@@ -18,6 +25,6 @@ pub const pin_config = ch32v.pins.GlobalConfiguration{
 
 /// Board-specific init: set 48 MHz clock, enable SysTick time
 pub fn init() void {
-    ch32v.clocks.init_48mhz_hsi();
+    ch32v.clocks.init(clock_config);
     ch32v.time.init();
 }
diff --git a/port/wch/ch32v/src/boards/nanoCH32V305.zig b/port/wch/ch32v/src/boards/nanoCH32V305.zig
@@ -5,7 +5,14 @@ pub const chip = @import("chip");
 pub const microzig = @import("microzig");
 const ch32v = microzig.hal;
 
-pub const cpu_frequency = 48_000_000; // 48 MHz
+/// Clock configuration for this board
+pub const clock_config: ch32v.clocks.Config = .{
+    .source = .hsi,
+    .target_frequency = 48_000_000,
+};
+
+/// CPU frequency is derived from clock config
+pub const cpu_frequency = clock_config.target_frequency;
 
 pub const pin_config = ch32v.pins.GlobalConfiguration{
     .GPIOA = .{
@@ -18,6 +25,6 @@ pub const pin_config = ch32v.pins.GlobalConfiguration{
 
 /// Board-specific init: set 48 MHz clock, enable SysTick time
 pub fn init() void {
-    ch32v.clocks.init_48mhz_hsi();
+    ch32v.clocks.init(clock_config);
     ch32v.time.init();
 }
diff --git a/port/wch/ch32v/src/hals/ch32v003.zig b/port/wch/ch32v/src/hals/ch32v003.zig
@@ -3,8 +3,13 @@ pub const peripherals = microzig.chip.peripherals;
 
 pub const pins = @import("ch32v003/pins.zig");
 pub const gpio = @import("ch32v003/gpio.zig");
+pub const clocks = @import("clocks.zig");
 pub const time = @import("time.zig");
 
+/// HSI (High Speed Internal) oscillator frequency
+/// This is the fixed internal RC oscillator frequency for CH32V003
+pub const hsi_frequency: u32 = 8_000_000; // 8 MHz
+
 // pub fn init() void {}
 
 const RCC = peripherals.RCC;
diff --git a/port/wch/ch32v/src/hals/ch32v103.zig b/port/wch/ch32v/src/hals/ch32v103.zig
@@ -5,8 +5,15 @@ pub const clocks = @import("clocks.zig");
 pub const time = @import("time.zig");
 pub const usart = @import("usart.zig");
 
+/// HSI (High Speed Internal) oscillator frequency
+/// This is the fixed internal RC oscillator frequency for CH32V103
+pub const hsi_frequency: u32 = 8_000_000; // 8 MHz
+
 /// Initialize HAL subsystems used by default
 /// CH32V103: set clock to 48 MHz via HSI PLL; SysTick driver differs on 103, so time is not enabled here.
 pub fn init() void {
-    clocks.init_48mhz_hsi();
+    clocks.init(.{
+        .source = .hsi,
+        .target_frequency = 48_000_000,
+    });
 }
diff --git a/port/wch/ch32v/src/hals/ch32v20x.zig b/port/wch/ch32v/src/hals/ch32v20x.zig
@@ -6,6 +6,10 @@ pub const clocks = @import("clocks.zig");
 pub const time = @import("time.zig");
 pub const usart = @import("usart.zig");
 
+/// HSI (High Speed Internal) oscillator frequency
+/// This is the fixed internal RC oscillator frequency for CH32V20x
+pub const hsi_frequency: u32 = 8_000_000; // 8 MHz
+
 pub const default_interrupts: microzig.cpu.InterruptOptions = .{
     // Default TIM2 handler provided by the HAL for 1ms timekeeping
     .TIM2 = time.tim2_handler,
diff --git a/port/wch/ch32v/src/hals/ch32v30x.zig b/port/wch/ch32v/src/hals/ch32v30x.zig
@@ -5,6 +5,10 @@ pub const clocks = @import("clocks.zig");
 pub const time = @import("time.zig");
 pub const usart = @import("usart.zig");
 
+/// HSI (High Speed Internal) oscillator frequency
+/// This is the fixed internal RC oscillator frequency for CH32V30x
+pub const hsi_frequency: u32 = 8_000_000; // 8 MHz
+
 /// Default interrupt handlers provided by the HAL
 pub const default_interrupts: microzig.cpu.InterruptOptions = .{
     .TIM2 = time.tim2_handler,
diff --git a/port/wch/ch32v/src/hals/clocks.zig b/port/wch/ch32v/src/hals/clocks.zig
diff --git a/port/wch/ch32v/src/hals/time.zig b/port/wch/ch32v/src/hals/time.zig
