vsdworks/README.html at main · arungithub007/vsdworks

819 lines (796 loc) · 39.3 KB
<!DOCTYPE html>
        <html>
        <head>
            <meta charset="UTF-8">
            <title>vsdworks</title>
            <style>
/* From extension vscode.github */
/*---------------------------------------------------------------------------------------------
 *  Copyright (c) Microsoft Corporation. All rights reserved.
 *  Licensed under the MIT License. See License.txt in the project root for license information.
 *--------------------------------------------------------------------------------------------*/
.vscode-dark img[src$=\#gh-light-mode-only],
.vscode-light img[src$=\#gh-dark-mode-only],
.vscode-high-contrast:not(.vscode-high-contrast-light) img[src$=\#gh-light-mode-only],
.vscode-high-contrast-light img[src$=\#gh-dark-mode-only] {
	display: none;
            <link rel="stylesheet" href="https://cdn.jsdelivr.net/npm/katex/dist/katex.min.css">
<link href="https://cdn.jsdelivr.net/npm/katex-copytex@latest/dist/katex-copytex.min.css" rel="stylesheet" type="text/css">
        <link rel="stylesheet" href="https://cdn.jsdelivr.net/gh/Microsoft/vscode/extensions/markdown-language-features/media/markdown.css">
<link rel="stylesheet" href="https://cdn.jsdelivr.net/gh/Microsoft/vscode/extensions/markdown-language-features/media/highlight.css">
            body {
                font-family: -apple-system, BlinkMacSystemFont, 'Segoe WPC', 'Segoe UI', system-ui, 'Ubuntu', 'Droid Sans', sans-serif;
                font-size: 14px;
                line-height: 1.6;
        </style>
        <style>
.task-list-item {
    list-style-type: none;
.task-list-item-checkbox {
    margin-left: -20px;
    vertical-align: middle;
    pointer-events: none;
  --color-note: #0969da;
  --color-tip: #1a7f37;
  --color-warning: #9a6700;
  --color-severe: #bc4c00;
  --color-caution: #d1242f;
  --color-important: #8250df;
@media (prefers-color-scheme: dark) {
    --color-note: #2f81f7;
    --color-tip: #3fb950;
    --color-warning: #d29922;
    --color-severe: #db6d28;
    --color-caution: #f85149;
    --color-important: #a371f7;
.markdown-alert {
  padding: 0.5rem 1rem;
  margin-bottom: 16px;
  color: inherit;
  border-left: .25em solid #888;
.markdown-alert>:first-child {
  margin-top: 0
.markdown-alert>:last-child {
  margin-bottom: 0
.markdown-alert .markdown-alert-title {
  display: flex;
  font-weight: 500;
  align-items: center;
  line-height: 1
.markdown-alert .markdown-alert-title .octicon {
  margin-right: 0.5rem;
  display: inline-block;
  overflow: visible !important;
  vertical-align: text-bottom;
  fill: currentColor;
.markdown-alert.markdown-alert-note {
  border-left-color: var(--color-note);
.markdown-alert.markdown-alert-note .markdown-alert-title {
  color: var(--color-note);
.markdown-alert.markdown-alert-important {
  border-left-color: var(--color-important);
.markdown-alert.markdown-alert-important .markdown-alert-title {
  color: var(--color-important);
.markdown-alert.markdown-alert-warning {
  border-left-color: var(--color-warning);
.markdown-alert.markdown-alert-warning .markdown-alert-title {
  color: var(--color-warning);
.markdown-alert.markdown-alert-tip {
  border-left-color: var(--color-tip);
.markdown-alert.markdown-alert-tip .markdown-alert-title {
  color: var(--color-tip);
.markdown-alert.markdown-alert-caution {
  border-left-color: var(--color-caution);
.markdown-alert.markdown-alert-caution .markdown-alert-title {
  color: var(--color-caution);
        </head>
        <body class="vscode-body vscode-dark">
            <h1 id="vsdworks">vsdworks</h1>
<p>This repository contains all the information required for the physical design flow of your IPs or SOCs, using qflow and other open-source tools. It was created during the &quot;Beginner Physical Design using Open-Source EDA Tools&quot; .</p>
<h2 id="table-of-content"><strong>TABLE OF CONTENT</strong></h2>
<blockquote>
<p><strong>1. DAY-1</strong></p>
</blockquote>
<p>PART-1 (INTERACTION WITH COMPUTER)</p>
<li>INTRODUCTION TO QFN-48</li>
<li>INTRODUCTION TO RISC-V</li>
<li>FROM S/W TO H/W APPLICATIONS</li>
<p>PART-2 (SOC DESIGN AND OPENLANE)</p>
<li>INTRODUCTION TO ALL OPEN SOURCE DEGITAL ASIC DESIGN</li>
<li>SIMPLIFIED RLT2GDS FLOW</li>
<li>INTRODUCTION TO OPENLANE AND STRIVE CHIPSET</li>
<li>INTRODUCTION TO OPENLAEN DETAILED ASIC DESIGN FLOW</li>
<p>PART-3 (GET FAMILIAR WITH OPEN SOURCE EDA)</p>
<li>OPENLADE DIRECTORY STRUCTURE IN DETAILS</li>
<li>DESIGN PREPARATION SETUP</li>
<li>RUN SYNTHESYS</li>
<li>OPENLANE PROJ GIT LINK DESCRIPTION</li>
<li>STEPS TO CHARACTERISE THE RESULT OF SYNTHESIS</li>
<blockquote>
<p><strong>DAY-2</strong></p>
</blockquote>
<blockquote>
<h1 id="day-1">DAY-1</h1>
</blockquote>
<h1 id="part-1-interaction-with-computer">PART-1 (INTERACTION WITH COMPUTER)</h1>
<h2 id="1-introduction-to-qfn-48">1. INTRODUCTION TO QFN-48</h2>
<h3 id="package-qfn-48">PACKAGE QFN-48</h3>
<p>The package are protective layer where ICs are put into to easy handing and assembling onto printed ciruite board to protect devices from damage.</p>
<p>Here, QFN-48 means Quad Flat No-leads which have 48 pins and surface_mount. A wide variety of electronic packages exist, including through-hole packages, surface mount packages, chip carriers, pin grid arrays, flat packages, and ball grid arrays.
Using these small packages we can place IC to a circuit board.</p>
<p>These are used in various applications as follows,</p>
<li>Automotive</li>
<li>Consumer electronics</li>
<li>Industrial and powe applocations ...etc.</li>
<p><img src="https://github.com/arungithub007/vsdworks/assets/95173376/681fcbb6-6838-4b4e-bda4-6b341f610083" alt="Screenshot 2024-04-26 084350"></p>
<p>The core is placed in the middle of the quad flat package. Here below is how the chip placed in the middle of the package looks like</p>
<p><strong>IC</strong> is the <strong>intergrated circuit</strong> which consist of millions of transistors, cpacitors, resigtors inside a semiconductor chip.
They comes in veriety of size and pakages.</p>
<p><strong>SOC - System on Chip</strong> is kind of IC which has the capability of combining functional elemnts of many electronic device on a single chip. It may constist of CPU, Memeory, inputs, outputs, ICs, IPs and other functional elements integrated init. SOC is used in multiple computing task, we can widely see in mobiles, laptops, tablets, AI devices etc.</p>
<p>The chip is madeup of <strong>core</strong> and <strong>die</strong> area.</p>
<p><strong>Die</strong> is the semiconductin_material(specimen) on which caore(fundamental logic circuit) is fabricated.</p>
<p><strong>Core</strong> is the section of chip where the fundamental logic of the design is placed.</p>
<p>The fabrication of the chip is done on the <strong>silicon wafer</strong> which are usually of 9 inch to 12 inch in diameter. Then, this wafer is cutted into pieces. Each piece has similar funtionality of the fundamental logic called <strong>Die</strong>.</p>
<p><img src="https://github.com/arungithub007/vsdworks/assets/95173376/16c96f7f-fb9e-4a51-8065-ea4c76d7cd79" alt="Screenshot 2024-04-26 091121"></p>
<p>We can make external connection by placing Pads on the rectangualer metal patches as in above fig.</p>
<h2 id="2-introduction-to-risc-v">2. INTRODUCTION TO RISC-V</h2>
<p>RISC-V stands as a public, open-source specification for an Instruction Set Architecture (ISA) based on Reduced Instruction Set Computer prinnciples, setting it apart from the proprietary ISAs such as x86, typically found in personal computers, and ARM, commonly used in mobile devices.
Unlike many ISAs that are bound by proprietary standards, RISC-V is accessible under licenses that are free of charge, giving it a significant advantage over its commercial counterparts. It’s characterized by its simplicity, stability, and compact standard base, while offering extendable ISA support. This has been instrumental in enhancing the adaptability, scalability, extensibility, and modular nature of chip designs.</p>
<h2 id="3-from-sw-to-hw-applications">3. FROM S/W TO H/W APPLICATIONS</h2>
<p><strong>Assembly language</strong> is the bridge betweeen s/w and h/w.
Different software and applications runs in different language programs(ex:- C, C++, Java, pyhton ...etc). Hardware cannot understand these lanuguages therefore we use special program like comiler and assembler to convert the instuctions in different languages to the targeted assembly language.</p>
<h1 id="part-2-soc-design-and-openlane">PART-2 (SOC DESIGN AND OPENLANE)</h1>
<h2 id="1-introduction-to-all-open-source-degital-asic-design">1. INTRODUCTION TO ALL OPEN SOURCE DEGITAL ASIC DESIGN</h2>
<p>Some of the open sources we can use for,</p>
<p>RTL Designs</p>
<li><a href="http://libracores.org">libracores.org</a></li>
<li><a href="http://opencores.org">opencores.org</a></li>
<li><a href="http://github.com">github.com</a></li>
<p>EDA tools</p>
<li>Qflow</li>
<li>OpenRoad</li>
<li>OpenLane</li>
<p>PDK data</p>
<li><a href="https://github.com/google/skywater-pdk">Google + skywater</a> = foss 130nm PDK</li>
<blockquote>
<p>PKD: <em>Process Desin Kit</em> is a collection of files used to model fabrication process by the EDA tools to design an IC.</p>
<blockquote>
<p>This is the interface between fabrication and designers</p>
</blockquote>
<p>The PDK includes:</p>
<li>PDRs: <em>process design rules</em> contained in DRC, LVS, PEX files.</li>
<li>Device Models.</li>
<li>Digital STD_Cell libs.</li>
<li>I/O libs.</li>
</blockquote>
<h2 id="2-simplified-rlt2gds-flow">2. SIMPLIFIED RLT2GDS FLOW</h2>
<h3 id="logic-synthesis">Logic Synthesis</h3>
<th style="text-align:left">no.</th>
<th style="text-align:left">Description</th>
<th style="text-align:left">tool</th>
<td style="text-align:left">i</td>
<td style="text-align:left">RTL synthesis using</td>
<td style="text-align:left">yosys</td>
<td style="text-align:left">ii</td>
<td style="text-align:left">Technology mapping using</td>
<td style="text-align:left">abc</td>
<td style="text-align:left">iii</td>
<td style="text-align:left">STA reports using</td>
<td style="text-align:left">OpenSTA</td>
<h3 id="floor-plan">Floor Plan</h3>
<th style="text-align:left">no.</th>
<th style="text-align:left">Description</th>
<th style="text-align:left">tool</th>
<td style="text-align:left">i</td>
<td style="text-align:left">To implement core area</td>
<td style="text-align:left">init_fp</td>
<td style="text-align:left">ii</td>
<td style="text-align:left">To place input,output ports and macros</td>
<td style="text-align:left">ioplacer</td>
<td style="text-align:left">iii</td>
<td style="text-align:left">To geerate the power description n/w</td>
<td style="text-align:left">pdn</td>
<td style="text-align:left">iv</td>
<td style="text-align:left">To insert welltap and Decap cells(physical only cells)</td>
<td style="text-align:left">tapcell</td>
<h3 id="placement">Placement</h3>
<th style="text-align:left">no.</th>
<th style="text-align:left">Description</th>
<th style="text-align:left">tool</th>
<td style="text-align:left">i</td>
<td style="text-align:left">To perform Global Placement</td>
<td style="text-align:left">RePlace</td>
<td style="text-align:left">ii</td>
<td style="text-align:left">To Perform Design Optimization</td>
<td style="text-align:left">Resizer</td>
<td style="text-align:left">iii</td>
<td style="text-align:left">To perform Timing Optimization</td>
<td style="text-align:left">OpenPhySyn</td>
<td style="text-align:left">iv</td>
<td style="text-align:left">To Perfrom Detailed Placement</td>
<td style="text-align:left">OpenDP</td>
<h3 id="cts">CTS</h3>
<th style="text-align:left">no.</th>
<th style="text-align:left">Description</th>
<th style="text-align:left">tool</th>
<td style="text-align:left">i</td>
<td style="text-align:left">To synthesize the CLK distribution n/w</td>
<td style="text-align:left">Triton CTS</td>
<h3 id="routing">Routing</h3>
<th style="text-align:left">no.</th>
<th style="text-align:left">Description</th>
<th style="text-align:left">tool</th>
<td style="text-align:left">i</td>
<td style="text-align:left">To perform Global rouitng</td>
<td style="text-align:left">FastRoute</td>
<td style="text-align:left">ii</td>
<td style="text-align:left">To perform detailed routing</td>
<td style="text-align:left">TritonRoute</td>
<td style="text-align:left">iii</td>
<td style="text-align:left">To Perform SPEF extraction</td>
<td style="text-align:left">SPEF-Extraction</td>
<h3 id="sta">STA</h3>
<th style="text-align:left">no.</th>
<th style="text-align:left">Description</th>
<th style="text-align:left">tool</th>
<td style="text-align:left">i</td>
<td style="text-align:left">To get STA reports</td>
<td style="text-align:left">OpenSTA</td>
<h3 id="gdsii-generation">GDSII Generation</h3>
<th style="text-align:left">no.</th>
<th style="text-align:left">Description</th>
<th style="text-align:left">tool</th>
<td style="text-align:left">i</td>
<td style="text-align:left">to perform final GDSII layout file from routed def</td>
<td style="text-align:left">magic</td>
<h3 id="checks">Checks</h3>
<th style="text-align:left">no.</th>
<th style="text-align:left">Description</th>
<th style="text-align:left">tool</th>
<td style="text-align:left">i</td>
<td style="text-align:left">To perform DRC checks and Antenna Checks</td>
<td style="text-align:left">Magic</td>
<td style="text-align:left">ii</td>
<td style="text-align:left">To perform LVS checks</td>
<td style="text-align:left">NetGen</td>
<h2 id="3-introduction-to-openlane-and-strive-chipset">3. INTRODUCTION TO OPENLANE AND STRIVE CHIPSET</h2>
<h2 id="4-introduction-to-openlaen-detailed-asic-design-flow">4. INTRODUCTION TO OPENLAEN DETAILED ASIC DESIGN FLOW</h2>
<h1 id="part-3-get-familiar-with-open-source-eda">PART-3 (GET FAMILIAR WITH OPEN SOURCE EDA)</h1>
<h2 id="1-openlane-directory-structure-in-details">1. OPENLANE DIRECTORY STRUCTURE IN DETAILS</h2>
<h3 id="importent-file-in-openlane_working_dir">Importent file in openlane_working_dir</h3>
<li>pdk file</li>
<li>openlane
<img src="https://github.com/arungithub007/vsdworks/assets/95173376/9f6a5290-4f74-4230-86f4-3a3fb2ad841f" alt="Screenshot 2024-04-27 092126"></li>
<p>The PDK we are usign here is Skywater130nm which is recently made as opensource. Openlane is built arround this pdk.</p>
<h3 id="firest-lets-see-pdk-file">Firest lets see PDK file:</h3>
<p><img src="https://github.com/arungithub007/vsdworks/assets/95173376/57f428aa-6cf2-4ff8-bc27-61c9c9006de8" alt="Screenshot 2024-04-27 092816"></p>
<p>ALL the files present in these pdk files are shown in the above directory structure.</p>
<p>The silicon foundry files i.e.,skywater130nm or any of the foundry files made to use in the commerrtial eda tools(Paid version) rather than opensource eda tools. This open_pdks used to avoid this problem by converting the files from commertial levl to opensource tool(for example like magic, netgen...etc) usable.</p>
<p>Sky130A is the foundry file that made opensource eda compatible.</p>
<th style="text-align:left">file</th>
<th style="text-align:left">description</th>
<th style="text-align:left">contents</th>
<td style="text-align:left">libs.ref</td>
<td style="text-align:left">it is specific to tecchnology. Here we are focusing on Sky130_fd_sc_hd</td>
<td style="text-align:left"><img src="https://github.com/arungithub007/vsdworks/assets/95173376/031f4959-abeb-467f-897b-8d0f4550173b" alt="Screenshot 2024-04-27 094803"></td>
<td style="text-align:left">libs.tech</td>
<td style="text-align:left">it is specific to tool</td>
<td style="text-align:left"><img src="https://github.com/arungithub007/vsdworks/assets/95173376/622a8665-cc4f-4160-8636-abb461289bbd" alt="Screenshot 2024-04-27 095010"></td>
<h4 id="sky130_fd_sc_hd-">sky130_fd_sc_hd :</h4>
<p>The file name abrivates as follows,</p>
<li>fd --&gt; foundry</li>
<li>sc --&gt; std_cells</li>
<li>hd --&gt; high dencity</li>
<p><img src="https://github.com/arungithub007/vsdworks/assets/95173376/9f4622c9-b51b-4deb-b470-b0715a7a606c" alt="Screenshot 2024-04-27 100040">
these are the files we can find inside the sky130_fd_sc_hd</p>
<h2 id="2-design-preparation-setup">2. DESIGN PREPARATION SETUP</h2>
<h3 id="openlane">openlane</h3>
<p>openlane is a silicon implimtntation platform that supports open-source tools such as yosys, Openroad, Macgic, Klayout along with other opensource and proprietary utilities.</p>
<p>These are the files present in openlane
<img src="https://github.com/arungithub007/vsdworks/assets/95173376/872d75aa-2580-4ff9-86ab-a6ddae667a71" alt="Screenshot 2024-04-27 123538"></p>
<h4 id="the-list-of-main-commands-we-use-here-are">The list of main commands we use here are:</h4>
<p><img src="https://github.com/arungithub007/vsdworks/assets/95173376/2b95a6e6-bca6-4508-b511-bf80859fb186" alt="Screenshot 2024-04-27 125606"></p>
<blockquote>
<p>note:- the commads from 3 to 14 can be put into a &lt;file_name&gt; and we can pass it to &quot;flow.tcl&quot; i.e, &gt; ./flow.tcl -interactive -file &lt;file_name&gt;</p>
</blockquote>
<h4 id="design-file">Design file</h4>
<p><strong>picorv32a</strong> is the Design we are using here. we can also create other desig aswell in the design folder of openlane.</p>
<p>Some list of designs we will get in design is shown in below:
<img src="https://github.com/arungithub007/vsdworks/assets/95173376/037bb8a5-5b14-4e97-b681-fe44f2d3d6eb" alt="Screenshot 2024-04-27 130713"></p>
<p>The files included in the <strong>picorv32a</strong> is as follows:
<img src="https://github.com/arungithub007/vsdworks/assets/95173376/21fb00d8-8258-4135-a3de-8f0a0d57bdcd" alt="Screenshot 2024-04-27 131531"></p>
<blockquote>
<p>note:- here config.tcl contains information about:</p>
<li>design name</li>
<li>path to sdc and .v</li>
<li>clock_period, cloc_port, clock_net</li>
</blockquote>
<h4 id="docker">DOCKER</h4>
<p><strong>First</strong> we need to get inside docker_build using command <em><strong>docker</strong></em> And get the docker into interactive mode.</p>
<blockquote>
<li>we should be in interactive mode ohter wise it will excicute full flow.</li>
<p><code>./flow.tcl -interactive</code></p>
<ol start="2">
<li>we need to include all the files required to run the flow</li>
<p><code>package require openlane 0.9</code></p>
</blockquote>
<p><img src="https://github.com/arungithub007/vsdworks/assets/95173376/9f5426cc-f717-42ca-aef4-a7130047b3d9" alt="Screenshot 2024-04-27 134121"></p>
<h4 id="design-setup-stage">Design setup stage:</h4>
<p><img src="https://github.com/arungithub007/vsdworks/assets/95173376/7fdbac9d-f76a-43a6-bc24-10b7a4d9f124" alt="Screenshot 2024-04-27 134420"></p>
<p>When we run  <code>prep -design picorv32a</code> a run file with todays date will be created inside the <code>Picorv32a&gt;runs&gt;dd-mm_hr-min</code>
<img src="https://github.com/arungithub007/vsdworks/assets/95173376/3fa75454-414d-4a52-8206-2da2465e6024" alt="image"></p>
<p>At this point we  can see multiple folders and files are created inside the <strong>27-04_08-06</strong> file. But most of them are empty.</p>
<p><img src="https://github.com/arungithub007/vsdworks/assets/95173376/5b4fa439-607e-465b-b036-a4a658fe12a6" alt="image"></p>
<p>Step by step each files will generated with report files inside these files.</p>
<p>Next we will start our synthesis</p>
<h2 id="3-run-synthesis">3. RUN SYNTHESIS</h2>
<p><code>run_synthesis</code>This will run the <code>yosys</code> and <code>abc</code> synthesis.
<img src="https://github.com/arungithub007/vsdworks/assets/95173376/25808d53-92b1-47e0-ae37-1025d423bf26" alt="image"></p>
<h2 id="4-openlane-proj-git-link-description">4. OPENLANE PROJ GIT LINK DESCRIPTION</h2>
<p><a href="https://github.com.efabless/openlane">https://github.com.efabless/openlane</a></p>
<h2 id="5-steps-to-characterise-the-result-of-synthesis">5. STEPS TO CHARACTERISE THE RESULT OF SYNTHESIS</h2>
<p>After synthesis report files are generated inside the synthesis folder present in runs. we can see the report mentioned above in these folders, as shown below.
<img src="https://github.com/arungithub007/vsdworks/assets/95173376/aada7452-7d7c-404d-b2bf-fad8a1449cf4" alt="image"></p>
<blockquote>
<h1 id="day-2">DAY-2</h1>
</blockquote>
<h1 id="part-1-chip-floor-planning-considerations">PART 1. Chip floor planning considerations</h1>
<h2 id="1-utilization-factor-and-aspect-ratio">1. Utilization factor and Aspect ratio</h2>
<h2 id="6-steps-to-run-floorplan">6. STEPS TO RUN FLOORPLAN</h2>
<p>Before sunning the floor plan just have a glan on <a href="http://README.html">README.md</a> file in openlane/configuration directory.
<img src="https://github.com/arungithub007/vsdworks/assets/95173376/93cd1ed4-352a-477e-8ccc-7f46b4587f70" alt="image"></p>
<blockquote>
<p>open openlane/configuration/floorplan.tcl where we can see default parameter set for floorplan by openlane.</p>
</blockquote>
<p>here we need to give more preority to  these files.
<img src="https://github.com/arungithub007/vsdworks/assets/95173376/cca85fdd-6a5a-46ed-92e5-13d97ad39e5d" alt="image"><img src="https://github.com/arungithub007/vsdworks/assets/95173376/1c654540-3197-4686-8111-e7fa03c96d0d" alt="image"></p>
<h2 id="7-steps-to-view-floorplan">7. steps to view floorplan</h2>
<p><img src="https://github.com/arungithub007/vsdworks/assets/95173376/dc8e3dad-8167-440d-80ab-04531988d4d8" alt="image"></p>
<h2 id="8-review-floorplan-in-magic">8. Review Floorplan in magic</h2>
<p><img src="https://github.com/arungithub007/vsdworks/assets/95173376/91e8a1c5-88a2-4564-b5ae-d9fae72aae26" alt="image"></p>
<p>we can get info of an object by selecting it and asking <strong>&gt;what</strong> in <em><strong>teckon</strong></em> as shown below.
<img src="https://github.com/arungithub007/vsdworks/assets/95173376/94555fe4-9b67-43b6-a1ef-30549fad7ce8" alt="image">
<img src="https://github.com/arungithub007/vsdworks/assets/95173376/4fb989cb-7256-45c3-968b-2954a49a82f7" alt="image"></p>
<h1 id="part-2-library-binding-and-placement">PART 2. Library Binding and Placement</h1>
<h2 id="congestion-aware-placement">Congestion aware placement</h2>
<p>The next stage after the floorplan is <em><strong>placement</strong></em>
to see placement in magic tools:
<img src="https://github.com/arungithub007/vsdworks/assets/95173376/c58e86e9-a04d-492a-9da4-c59e67e6d332" alt="image"></p>
<p><img src="https://github.com/arungithub007/vsdworks/assets/95173376/ad44a51c-79f1-410b-a77d-07d528922e7b" alt="image">
We can see All the std_cells placed in std_cells rows. All the physical only cells also place.</p>
<h1 id="part-3-cell-design-and-characterization-flow">PART 3. Cell design and characterization flow</h1>
<h1 id="part-4-general-timing-charactorization-parameters">PART 4. General timing charactorization parameters</h1>
<h1 id="steps-to-disply-std_cells-uisng-magic-tool">Steps to Disply std_cells Uisng Magic tool</h1>
<p>first we need to get the technology file from <code>sky130A</code> pdk folder, to the <code>vsdstdcelldesign</code> folder.
<img src="https://github.com/arungithub007/vsdworks/assets/95173376/ae2bc165-50b5-4130-be8f-383255e7f72e" alt="image"></p>
<p>now give magic tool command to display the cell</p>
<blockquote>
<p>magic -T sky130A.tech sky130_inv.mag</p>
</blockquote>
<p>The inevertor std_cell will be displayed as below.
<img src="https://github.com/arungithub007/vsdworks/assets/95173376/6cacb50b-a174-4bb2-90ad-5367cdb8331e" alt="image"></p>
<h1 id="introduction-to-sky130-basic-layers-and-lef-using-inerter">Introduction to sky130 basic layers and Lef using inerter</h1>
<p><img src="https://github.com/arungithub007/vsdworks/assets/95173376/0ff7899a-60e8-4fb8-a28d-0b0c45ac701f" alt="image">
we can use tkcon to get the infrmation about the cell layers by giving command <code>what</code>.</p>
<h1 id="creat-std-cell-layout-and-extract-spice-netlist">Creat std cell layout and extract SPICE netlist</h1>
<p>first we need to create spice file for our Invertor.
<code>tcl ext2spice cthresh 0 rthresh 0 ext2spice </code>
this will create new .spice file in our vsdstdcelldesign file
<img src="https://github.com/arungithub007/vsdworks/assets/95173376/8fdaba52-ad5b-4ab0-b691-0cba688e8a43" alt="image"></p>
<p><img src="https://github.com/arungithub007/vsdworks/assets/95173376/1e8926e4-e0e5-4cbd-b114-38b2f12a4fc0" alt="image"></p>
<p>Grids are used for easy measure.
<code>box</code> in tckon to get the measurment of the grid</p>
<p><img src="https://github.com/arungithub007/vsdworks/assets/95173376/5cb5d471-23ca-4d65-9fbc-ef635f1a8fbc" alt="image"></p>
<p>Make required modification in spice file.
<img src="https://github.com/arungithub007/vsdworks/assets/95173376/2ebb2c3e-8bfd-4826-b37d-363e67533f1e" alt="image"></p>
<p>we need to ru this in ngspice using <code>ngsipce &lt;source file name&gt;</code></p>
<p><img src="https://github.com/arungithub007/vsdworks/assets/95173376/0926be7b-f6c6-4327-9bb2-2be04fb985f5" alt="image"></p>
<p>Now to see plot use command in spice as below:</p>
<blockquote>
<p>plot y vs time a</p>
</blockquote>
<p><img src="https://github.com/arungithub007/vsdworks/assets/95173376/b1d410d1-986f-446f-b005-1004ac010c14" alt="image">
this is our transiant response</p>
<p>Now we need to charectorize the cell. means we need to derive value of 4 parameters.</p>
<p>value of rise transition
<img src="https://github.com/arungithub007/vsdworks/assets/95173376/5931ff43-dc97-4d5a-9dd6-756ad6bebff4" alt="image">
<img src="https://github.com/arungithub007/vsdworks/assets/95173376/a56d84ad-248e-42f4-b8ac-26d4c6fa32d9" alt="image">
diff b/w x0 should give raise time:</p>
<blockquote>
<p>(2.19701e-09) - (2.15231e-09) = 0.0447ns</p>
</blockquote>
<p>value of fall transition</p>
<blockquote>
<p>(4.06584e-9) - (4.0401e-9) = 0.02574ns</p>
</blockquote>
<p>fall cell delay</p>
<blockquote>
<p>(4.05284e-9)-(4.05052e-9)=0.00228ns</p>
</blockquote>
<p>rise cell delay</p>
<blockquote>
<p>(2.18e-9) - (2.15e-9) = 0.03ns</p>
</blockquote>
<h1 id="instruction-to-sky130-pdks-and-steps-to-download">Instruction to sky130 pdk's and steps to download</h1>
<p>download the files from git
<code>wget http://opencircuitdesign.com/open_pdks/archive/drc_tests.tg </code></p>
<p><img src="https://github.com/arungithub007/vsdworks/assets/95173376/d1ea8ec9-5eb8-432e-8497-a1abaa059b09" alt="image"></p>
<p>To open the magic tool use:</p>
<blockquote>
<p>magic -d XR</p>
</blockquote>
<p>then open metal3.meg file
<img src="https://github.com/arungithub007/vsdworks/assets/95173376/11c6eede-d05d-4c07-8522-b8c43762df0b" alt="image"></p>
<p><img src="https://github.com/arungithub007/vsdworks/assets/95173376/9c6ebda8-693f-4693-b92b-e6215109a387" alt="image"></p>
<p>To make a via :
select a area &gt; select the maetal layer &gt; set the via using <code>cif see VIA2</code>
<img src="https://github.com/arungithub007/vsdworks/assets/95173376/e216634b-a6e1-4a28-8119-cb0bbeb06b70" alt="image"></p>
<h1 id="incorrect-poly9">incorrect poly.9</h1>
<p><img src="https://github.com/arungithub007/vsdworks/assets/95173376/c6779364-63fe-4d6c-9cfe-bb18ae5cfb43" alt="image">
to correct the error we need to go to sky130.tech file</p>
<p>add the spacing
<img src="https://github.com/arungithub007/vsdworks/assets/95173376/2595cd95-f1e3-46e0-9f86-2879f81691fc" alt="image"></p>
<p>then, source the tech file again.
<img src="https://github.com/arungithub007/vsdworks/assets/95173376/48fa6853-d618-456c-8529-8a301cafa8d6" alt="image"></p>
<h1 id="lab-challenge-to-cdescribe-the-drc-error-as-geometrical-construct">Lab challenge to c=describe the DRC error as geometrical construct</h1>
<p><img src="https://github.com/arungithub007/vsdworks/assets/95173376/cee9237a-d1c8-4f27-9885-9923a0df1adc" alt="image"></p>
<p><img src="https://github.com/arungithub007/vsdworks/assets/95173376/0fb8c0ea-16b6-4a51-b65e-ae4b21faf15f" alt="image"></p>
<p>vendor drc rules
<img src="https://github.com/arungithub007/vsdworks/assets/95173376/e22f32f1-829a-4e93-af14-6971cef35978" alt="image"></p>
<h2 id="modified-nwell-under-vendor-drc-rules">modified nwell under vendor drc rules
<img src="https://github.com/arungithub007/vsdworks/assets/95173376/61c67601-5516-4422-af00-52a31a5d2bd1" alt="image"></h2>
<p>style drc
<img src="https://github.com/arungithub007/vsdworks/assets/95173376/ca843205-90e3-4292-871f-ee117825527b" alt="image">
modified style drc
<img src="https://github.com/arungithub007/vsdworks/assets/95173376/9f326412-1e70-4021-8de5-ff9142d438ec" alt="image"></p>
<p><img src="https://github.com/arungithub007/vsdworks/assets/95173376/0fba0017-11af-4186-beda-89c0c57b0503" alt="image"></p>
<p>problem is solved by adding <em><strong>nsubstratecontact</strong></em>
<img src="https://github.com/arungithub007/vsdworks/assets/95173376/952c3e2e-6cf3-45f5-9abb-9c8f318ce1fe" alt="image">
<img src="https://github.com/arungithub007/vsdworks/assets/95173376/e5d1ab24-05d1-455e-88d8-287057b74630" alt="image"></p>
<h1 id="day-4-pre-layout-analysis-and-importance-of-good-clock-tree">Day 4 Pre layout analysis and importance of good clock tree</h1>
<h2 id="steps-to-convert-grid-info-to-track-info">Steps to convert grid info to track info</h2>
<h3 id="first-objective-is-to-extract-lef-file-from-mag-file">first objective is to extract lef file from .mag file</h3>
<p>Then, the extracted lef file is plugged into <em><strong>picorv32flow</strong></em></p>
<p><img src="https://github.com/arungithub007/vsdworks/assets/95173376/2cf94f50-d2ad-4f45-8e92-1c6cd16b0582" alt="image">
these are teck info, used during <em><strong>routing stage</strong></em>.</p>
<p><img src="https://github.com/arungithub007/vsdworks/assets/95173376/1aa4b7f9-d84e-4876-bfc8-bbd44b0906c1" alt="image">
li1 is the locali we can see in lable A and Y.</p>
<p><img src="https://github.com/arungithub007/vsdworks/assets/95173376/beaf5cf2-256c-4b7a-ae2b-915a716d82d2" alt="image">
now we have converted Grid definition according to track.</p>
<h3 id="second-objective-is-to-convert-magic-layout-to-std-cell-lef">second objective is to convert magic layout to std cell lef</h3>
<p>width of the std cells must be odd multiple of x pitch.
<img src="https://github.com/arungithub007/vsdworks/assets/95173376/9d926e9e-ed34-45a2-a457-53f17ec3aa4d" alt="image">
same goes for height also.</p>
<h4 id="now-we-can-see-how-to-convert-label-to-ports">now we can see how to convert label to ports.</h4>
<p><img src="https://github.com/arungithub007/vsdworks/assets/95173376/9deb22c9-1950-4672-94ae-48dd5ff65411" alt="image">
this is how we can create the ports usinf label for A. similerly we can do for all the ports.
we need to be carefull while attaching to layer. In label-A and Y, the attach to layer is <em><strong>locali</strong></em> . But for others it may be metal1, metal2 ..etc. like that.</p>
<p><img src="https://github.com/arungithub007/vsdworks/assets/95173376/1562eb64-0a88-4348-a68f-e815e94577a9" alt="image">
save the layout with our own costum name. i have given sky130_vsdinv.mag.</p>
<p>After creating the sky13_vsdinv.mag open it in magic tool. do <code>lef write</code>, wwhich create leaf file is the same directory.
<img src="https://github.com/arungithub007/vsdworks/assets/95173376/d6bf9814-b669-4cc7-8a08-64fb95b090a4" alt="image"></p>
<p>lef file contains the modifications we have done.
<img src="https://github.com/arungithub007/vsdworks/assets/95173376/ffcf78d5-4170-49a4-9202-3b56c30c88c8" alt="image">
<img src="https://github.com/arungithub007/vsdworks/assets/95173376/4e755966-e7cf-4f95-81f4-3002e308b7a9" alt="image"></p>
<blockquote>
<p>Now we have to move these files to our design src files. So that all our design files present in a single group.</p>
</blockquote>
<blockquote>
<p>Now one more fiel we need to cp is
<img src="https://github.com/arungithub007/vsdworks/assets/95173376/39df7d64-c4bf-4283-a25c-9221cb6cf9a4" alt="image"></p>
<p>after copiying all files our src file will look like this
<img src="https://github.com/arungithub007/vsdworks/assets/95173376/32fbf048-2612-40f3-8d44-4d6cc3f44604" alt="image"></p>
</blockquote>
<p><img src="https://github.com/arungithub007/vsdworks/assets/95173376/69ce039e-114b-403d-b9e1-64a72f0a02f6" alt="image">
now that we have added the file, we have to run the reguler flow commands i.e., from docker to synthesis.. floorplan...etc.</p>
<p><img src="https://github.com/arungithub007/vsdworks/assets/95173376/3fb1838a-e28f-48b1-818a-7c9bae4a84ff" alt="image"></p>
<blockquote>
<p>run_synthesis</p>
</blockquote>
<p><img src="https://github.com/arungithub007/vsdworks/assets/95173376/c5273831-aa22-4f75-89a1-5493b16b280d" alt="image"></p>
<p>To improve the timing and run synthesis
<p>prep -design picorv32a -tag 24-03_10-03 -overwrite</p>
<p>set lefs [glob $::env(DESIGN_DIR)/src/*.lef]
add_lefs -src $lefs</p>
<p>echo $::env(SYNTH_STRATEGY)</p>
<p>set ::env(SYNTH_STRATEGY) &quot;DELAY 3&quot;</p>
<p>echo $::env(SYNTH_BUFFERING)</p>
<p>echo $::env(SYNTH_SIZING)</p>
<p>set ::env(SYNTH_SIZING) 1</p>
<p>echo $::env(SYNTH_DRIVING_CELL)</p>
<p>run_synthesis
<img src="https://github.com/arungithub007/vsdworks/assets/95173376/a40d9ee0-cc42-4b1c-b34e-9cd13a447a5c" alt="image"></p>
<p>Check if vsd_inverter is added after the floorplan stage. Check layout after the placement_stage.
<img src="https://github.com/arungithub007/vsdworks/assets/95173376/fbf19cfc-8790-4644-a8ed-23b264d051c3" alt="image">
the above can be seen in merged.lef file in runs/03-5_12_15/tmp/merged.lef.</p>
<p>after running the run_placement, open the placement using magic tool. Then search for our <em><strong>sky130_vsdinv</strong></em> by zooming in.
<img src="https://github.com/arungithub007/vsdworks/assets/95173376/b8880c2b-64b6-4192-b69e-e38b5f5c9842" alt="image">
<img src="https://github.com/arungithub007/vsdworks/assets/95173376/dc78b6ca-0da8-4d8a-bd1a-b0aaecb5864c" alt="image">
the '<em>adutment</em>' is to ensure the power and ground is shared between cells.</p>
<p>when we expand the vsdinv cell we can see the connection between metal layers of our vsdinv cell and the abuted cells.
<img src="https://github.com/arungithub007/vsdworks/assets/95173376/614bce0c-52ac-451b-893c-57169f5c3307" alt="image"></p>
<h1 id="to-configure-opensta-for-post-timing-analysis">To configure OpenSTA for post timing analysis</h1>
<p>create a file named pre_sta.conf in openlane directory.
<img src="https://github.com/arungithub007/vsdworks/assets/95173376/b22252ac-1688-4858-801e-30a971e40147" alt="image"></p>
<p>We can see our cell's pin capacitance in *typical.lib file
<img src="https://github.com/arungithub007/vsdworks/assets/95173376/c5aec2e7-045f-4994-9efc-acfc7d2c2b04" alt="image"></p>
<p>we have to create a file called my_base.scd in src file of design.
<img src="https://github.com/arungithub007/vsdworks/assets/95173376/0401d8cb-eeea-4419-b738-d45aae289add" alt="image"></p>
<p>the above my_base.scd is written by taking the reference of base.sdc fiel in openlane scripts.
<img src="https://github.com/arungithub007/vsdworks/assets/95173376/3bd87267-f691-495e-a5cd-5c0e3c39a5cf" alt="image"></p>
<p><img src="https://github.com/arungithub007/vsdworks/assets/95173376/f3e84329-b6de-4024-bda9-4da671dfc0af" alt="image">
this the file where we are going to do STA.</p>
<p>use command:</p>
<blockquote>
<p>sta pre_sta.conf</p>
</blockquote>
<p>we can get the report of the nets using:</p>
<blockquote>
<p>report_net -connections <em>net_instance_name</em>
replace_cell instace lib_cell
report_checks -fileds {net cap slew input_pins} -digits 4
<img src="https://github.com/arungithub007/vsdworks/assets/95173376/4d4f097a-2fee-41ed-b608-89cbebb740ce" alt="image"></p>
</blockquote>
<p>by replacing the currect cell we can reduce the slack and get the report again.
<img src="https://github.com/arungithub007/vsdworks/assets/95173376/09645f8a-c71d-4628-a197-530175d432e7" alt="image"></p>
<p>After reducing the slack value to 0 or almost 0. we should rewite the old design.v file with the newly modified one. For that we use <em><strong>write</strong></em> command with path to design file with name, which will replace the old design file with new one.</p>
<blockquote>
<p>%write_verilog /home/vsduser/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/03-05_12-25/results/synthesis/picorv32a.synthesis.v</p>
</blockquote>
<p>then we can exit OpenSTA</p>
<p>After rewriting the netlist in openSTA we shouldnt run the synthesis again bcz it will create new netlist.</p>
<blockquote>
<li>Therefore now next step is to run_floorplan. So that it takes the updated netlist.</li>
<li>run_placement</li>
</blockquote>
<h1 id="run-cts">Run CTS</h1>
<p>After getting to placement stage of updated netlist we need to run CTS.</p>
<blockquote>
<p>run_cts</p>
</blockquote>
<p>this may take some time to run. then it will create cts file in synthesis file inside results.
<img src="https://github.com/arungithub007/vsdworks/assets/95173376/42c6338a-69e9-4197-9bc8-68a8a200befa" alt="image"></p>
<p>To know what are the arguments the our cts will check we need to go for cts.tcl in command file of openlane.
<img src="https://github.com/arungithub007/vsdworks/assets/95173376/158b846f-3692-420a-bed4-e09f01a72c0d" alt="image">
<img src="https://github.com/arungithub007/vsdworks/assets/95173376/fb7ad996-26e7-45ea-9953-9c8600a1b250" alt="image">
here the main thing we need to look is for openroad.</p>
<p>these are the tcl files we can see in the openroad.
<img src="https://github.com/arungithub007/vsdworks/assets/95173376/20908472-1a1e-4af9-804e-f2069ea7b663" alt="image"></p>
<p>Here we cannot see the synthesis part bcz openlane normally dosnt involve the synthesis in the process if we look into the openlane flow.</p>
<h3 id="post-cts-openroad-timing-analysis">Post-CTS OpenROAD timing analysis.</h3>
<p>The next stages are power distribution and Routing. Both will use the .def file.</p>
<p>Since openlace is integrated with openlane. we can access openroad in the openlane.
<img src="https://github.com/arungithub007/vsdworks/assets/95173376/94a8c23c-704e-41e2-8894-02d985b92e69" alt="image">
Now we can do Timing analysis here itself.</p>
openroad</p>
<p>read_lef /openLANE_flow/designs/picorv32a/runs/30-04_05-57/tmp/merged.lef</p>
<p>read_def /openLANE_flow/designs/picorv32a/runs/30-04_05-57/results/cts/picorv32a.cts.def</p>
<p>write_db pico_cts.db</p>
<p>read_db pico_cts.db</p>
<p>read_verilog /openLANE_flow/designs/picorv32a/runs/30-04_05-57/results/synthesis/picorv32a.synthesis_cts.v</p>
<p>read_liberty $::env(LIB_SYNTH_COMPLETE)</p>
<p>link_design picorv32a</p>
<p>read_sdc /openLANE_flow/designs/picorv32a/src/my_base.sdc</p>
<p>set_propagated_clock [all_clocks]</p>
<p>help report_checks</p>
<p>report_checks -path_delay min_max -fields {slew trans net cap input_pins} -format full_clock_expanded -digits 4</p>
            <script async src="https://cdn.jsdelivr.net/npm/katex-copytex@latest/dist/katex-copytex.min.js"></script>
        </body>
        </html>
Provide feedback

Saved searches

Use saved searches to filter your results more quickly

FilesExpand file tree

README.html

Latest commit

History

README.html

File metadata and controls
