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pokemon.map.smsg
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10 lines (10 loc) · 2.78 KB
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Warning (10273): Verilog HDL warning at HexDriver.sv(23): extended using "x" or "z" File: C:/ece385/FinalProject/HexDriver.sv Line: 23
Info (10281): Verilog HDL Declaration information at pokemon.sv(17): object "KEY" differs only in case from object "key" in the same scope File: C:/ece385/FinalProject/pokemon.sv Line: 17
Info (10281): Verilog HDL Declaration information at nios_system_mm_interconnect_0_router_003.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope File: C:/ece385/FinalProject/nios_system/synthesis/submodules/nios_system_mm_interconnect_0_router_003.sv Line: 48
Info (10281): Verilog HDL Declaration information at nios_system_mm_interconnect_0_router_003.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope File: C:/ece385/FinalProject/nios_system/synthesis/submodules/nios_system_mm_interconnect_0_router_003.sv Line: 49
Info (10281): Verilog HDL Declaration information at nios_system_mm_interconnect_0_router_002.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope File: C:/ece385/FinalProject/nios_system/synthesis/submodules/nios_system_mm_interconnect_0_router_002.sv Line: 48
Info (10281): Verilog HDL Declaration information at nios_system_mm_interconnect_0_router_002.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope File: C:/ece385/FinalProject/nios_system/synthesis/submodules/nios_system_mm_interconnect_0_router_002.sv Line: 49
Info (10281): Verilog HDL Declaration information at nios_system_mm_interconnect_0_router_001.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope File: C:/ece385/FinalProject/nios_system/synthesis/submodules/nios_system_mm_interconnect_0_router_001.sv Line: 48
Info (10281): Verilog HDL Declaration information at nios_system_mm_interconnect_0_router_001.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope File: C:/ece385/FinalProject/nios_system/synthesis/submodules/nios_system_mm_interconnect_0_router_001.sv Line: 49
Info (10281): Verilog HDL Declaration information at nios_system_mm_interconnect_0_router.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope File: C:/ece385/FinalProject/nios_system/synthesis/submodules/nios_system_mm_interconnect_0_router.sv Line: 48
Info (10281): Verilog HDL Declaration information at nios_system_mm_interconnect_0_router.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope File: C:/ece385/FinalProject/nios_system/synthesis/submodules/nios_system_mm_interconnect_0_router.sv Line: 49