-
Notifications
You must be signed in to change notification settings - Fork 1
Expand file tree
/
Copy pathvTBgenerator.py
More file actions
213 lines (172 loc) · 5.8 KB
/
vTBgenerator.py
File metadata and controls
213 lines (172 loc) · 5.8 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
#! /usr/bin/env python
'''
vTbgenerator.py -- generate verilog module Testbench
generated bench file like this:
fifo_sc #(
.DATA_WIDTH ( 8 ),
.ADDR_WIDTH ( 8 )
)
u_fifo_sc (
.CLK ( CLK ),
.RST_N ( RST_N ),
.RD_EN ( RD_EN ),
.WR_EN ( WR_EN ),
.DIN ( DIN [DATA_WIDTH-1 :0] ),
.DOUT ( DOUT [DATA_WIDTH-1 :0] ),
.EMPTY ( EMPTY ),
.FULL ( FULL )
);
Usage:
python vTbgenerator.py ModuleFileName.v
'''
import re
import sys
def delComment( Text ):
""" removed comment """
single_line_comment = re.compile(r"//(.*)$", re.MULTILINE)
multi_line_comment = re.compile(r"/\*(.*?)\*/",re.DOTALL)
Text = multi_line_comment.sub('\n',Text)
Text = single_line_comment.sub('\n',Text)
return Text
def delBlock( Text ) :
""" removed task and function block """
Text = re.sub(r'\Wtask\W[\W\w]*?\Wendtask\W','\n',Text)
Text = re.sub(r'\Wfunction\W[\W\w]*?\Wendfunction\W','\n',Text)
return Text
def findName(inText):
""" find module name and port list"""
p = re.search(r'([a-zA-Z_][a-zA-Z_0-9]*)\s*',inText)
mo_Name = p.group(0).strip()
return mo_Name
def paraDeclare(inText ,portArr) :
""" find parameter declare """
pat = r'\s'+ portArr + r'\s[\w\W]*?;'
ParaList = re.findall(pat ,inText)
return ParaList
def portDeclare(inText ,portArr) :
"""find port declare, Syntax:
input [ net_type ] [ signed ] [ range ] list_of_port_identifiers
return list as : (port, [range])
"""
port_definition = re.compile(
r'\b' + portArr +
r''' (\s+(wire|reg)\s+)* (\s*signed\s+)* (\s*\[.*?:.*?\]\s*)*
(?P<port_list>.*?)
(?= \binput\b | \boutput\b | \binout\b | ; | \) )
''',
re.VERBOSE|re.MULTILINE|re.DOTALL
)
pList = port_definition.findall(inText)
t = []
for ls in pList:
if len(ls) >=2 :
t = t+ portDic(ls[-2:])
return t
def portDic(port) :
"""delet as : input a =c &d;
return list as : (port, [range])
"""
pRe = re.compile(r'(.*?)\s*=.*', re.DOTALL)
pRange = port[0]
pList = port[1].split(',')
pList = [ i.strip() for i in pList if i.strip() !='' ]
pList = [(pRe.sub(r'\1', p), pRange.strip() ) for p in pList ]
return pList
def formatPort(AllPortList,isPortRange =1) :
PortList = AllPortList[0] + AllPortList[1] + AllPortList[2]
str =''
if PortList !=[] :
l1 = max([len(i[0]) for i in PortList])+2
l2 = max([len(i[1]) for i in PortList])
l3 = max(24, l1)
strList = []
for pl in AllPortList :
if pl != [] :
str = ',\n'.join( [' '*4+'.'+ i[0].ljust(l3)
+ '( '+ (i[0].ljust(l1 )+i[1].ljust(l2))
+ ' )' for i in pl ] )
strList = strList + [ str ]
str = ',\n\n'.join(strList)
return str
def formatDeclare(PortList,portArr, initial = "" ):
str =''
if initial !="" :
initial = " = " + initial
if PortList!=[] :
str = '\n'.join( [ portArr.ljust(4) +' '+(i[1]+min(len(i[1]),1)*' '
+i[0]).ljust(36)+ initial + ' ;' for i in PortList])
return str
def formatPara(ParaList) :
paraDec = ''
paraDef = ''
if ParaList !=[]:
s = '\n'.join( ParaList)
pat = r'([a-zA-Z_][a-zA-Z_0-9]*)\s*=\s*([\w\W]*?)\s*[;,]'
p = re.findall(pat,s)
l1 = max([len(i[0] ) for i in p])
l2 = max([len(i[1] ) for i in p])
paraDec = '\n'.join( ['parameter %s = %s;'
%(i[0].ljust(l1 +1),i[1].ljust(l2 ))
for i in p])
paraDef = '#(\n' +',\n'.join( [' .'+ i[0].ljust(l1 +1)
+ '( '+ i[1].ljust(l2 )+' )' for i in p])+ '\n)\n'
return paraDec,paraDef
def writeTestBench(input_file):
""" write testbench to file """
inFile = open(input_file)
inText = inFile.read()
# removed comment,task,function
inText = delComment(inText)
inText = delBlock (inText)
# moduel ... endmodule #
moPos_begin = re.search(r'(\b|^)module\b', inText ).end()
moPos_end = re.search(r'\bendmodule\b', inText ).start()
inText = inText[moPos_begin:moPos_end]
name = findName(inText)
paraList = paraDeclare(inText,'parameter')
paraDec , paraDef = formatPara(paraList)
ioPadAttr = [ 'input','output','inout']
input = portDeclare(inText,ioPadAttr[0])
output = portDeclare(inText,ioPadAttr[1])
inout = portDeclare(inText,ioPadAttr[2])
portList = formatPort( [input , output , inout] )
input = formatDeclare(input ,'reg', '0' )
output = formatDeclare(output ,'wire')
inout = formatDeclare(inout ,'wire')
# write testbench
timescale = '`timescale 1 ns / 100 ps\n'
print("//~ `default_nettype none")
print(timescale)
print("module %s_tb();" % name)
# module_parameter_port_list
print(paraDec)
# list_of_port_declarations
print("// %s Inputs\n%s\n" % (name, input ))
print("// %s Outputs\n%s\n" % (name, output))
print("// %s Bidirs\n%s\n" % (name, inout ))
# print clock
clk_rst = '''
initial
begin
//$shm_open ("db_name", is_sequence_time, db_size, is_compression, incsize,incfiles);
$shm_open ("dump.shm");
$shm_probe( "AC");
end
initial
begin
clk= 1;
forever #10 clk=~clk;
end
initial
begin
reset_b = 1;
#25 reset_b = 0;
#100 reset_b = 1;
end
'''
print(clk_rst)
# UUT
print("%s %s u_%s (\n%s\n);" %(name,paraDef,name,portList))
print("endmodule")
if __name__ == '__main__':
writeTestBench(sys.argv[1])