/*

* Copyright (C) 2009, 2010 Apple Inc. All rights reserved.

* Copyright (C) 2010 University of Szeged

*

* Redistribution and use in source and binary forms, with or without

* modification, are permitted provided that the following conditions

* are met:

* 1. Redistributions of source code must retain the above copyright

* notice, this list of conditions and the following disclaimer.

* 2. Redistributions in binary form must reproduce the above copyright

* notice, this list of conditions and the following disclaimer in the

* documentation and/or other materials provided with the distribution.

*

* THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY

* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR

* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL APPLE INC. OR

* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,

* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,

* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR

* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY

* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

*/

#ifndef ARMAssembler_h

#define ARMAssembler_h

#if ENABLE(ASSEMBLER) && CPU(ARM_THUMB2)

#include "AssemblerBuffer.h"

#include <wtf/Assertions.h>

#include <wtf/Vector.h>

#include <stdint.h>

namespace JSC {

namespace ARMRegisters {

typedef enum {

r0,

r1,

r2,

r3,

r4,

r5,

r6,

r7, wr = r7, // thumb work register

r8,

r9, sb = r9, // static base

r10, sl = r10, // stack limit

r11, fp = r11, // frame pointer

r12, ip = r12,

r13, sp = r13,

r14, lr = r14,

r15, pc = r15,

} RegisterID;

typedef enum {

s0,

s1,

s2,

s3,

s4,

s5,

s6,

s7,

s8,

s9,

s10,

s11,

s12,

s13,

s14,

s15,

s16,

s17,

s18,

s19,

s20,

s21,

s22,

s23,

s24,

s25,

s26,

s27,

s28,

s29,

s30,

s31,

} FPSingleRegisterID;

typedef enum {

d0,

d1,

d2,

d3,

d4,

d5,

d6,

d7,

d8,

d9,

d10,

d11,

d12,

d13,

d14,

d15,

d16,

d17,

d18,

d19,

d20,

d21,

d22,

d23,

d24,

d25,

d26,

d27,

d28,

d29,

d30,

d31,

} FPDoubleRegisterID;

typedef enum {

q0,

q1,

q2,

q3,

q4,

q5,

q6,

q7,

q8,

q9,

q10,

q11,

q12,

q13,

q14,

q15,

q16,

q17,

q18,

q19,

q20,

q21,

q22,

q23,

q24,

q25,

q26,

q27,

q28,

q29,

q30,

q31,

} FPQuadRegisterID;

inline FPSingleRegisterID asSingle(FPDoubleRegisterID reg)

{

ASSERT(reg < d16);

return (FPSingleRegisterID)(reg << 1);

}

inline FPDoubleRegisterID asDouble(FPSingleRegisterID reg)

{

ASSERT(!(reg & 1));

return (FPDoubleRegisterID)(reg >> 1);

}

}

class ARMv7Assembler;

class ARMThumbImmediate {

friend class ARMv7Assembler;

typedef uint8_t ThumbImmediateType;

static const ThumbImmediateType TypeInvalid = 0;

static const ThumbImmediateType TypeEncoded = 1;

static const ThumbImmediateType TypeUInt16 = 2;

typedef union {

int16_t asInt;

struct {

unsigned imm8 : 8;

unsigned imm3 : 3;

unsigned i : 1;

unsigned imm4 : 4;

};

// If this is an encoded immediate, then it may describe a shift, or a pattern.

struct {

unsigned shiftValue7 : 7;

unsigned shiftAmount : 5;

};

struct {

unsigned immediate : 8;

unsigned pattern : 4;

};

} ThumbImmediateValue;

// byte0 contains least significant bit; not using an array to make client code endian agnostic.

typedef union {

int32_t asInt;

struct {

uint8_t byte0;

uint8_t byte1;

uint8_t byte2;

uint8_t byte3;

};

} PatternBytes;

ALWAYS_INLINE static void countLeadingZerosPartial(uint32_t& value, int32_t& zeros, const int N)

{

if (value & ~((1 << N) - 1)) /* check for any of the top N bits (of 2N bits) are set */

value >>= N; /* if any were set, lose the bottom N */

else /* if none of the top N bits are set, */

zeros += N; /* then we have identified N leading zeros */

}

static int32_t countLeadingZeros(uint32_t value)

{

if (!value)

return 32;

int32_t zeros = 0;

countLeadingZerosPartial(value, zeros, 16);

countLeadingZerosPartial(value, zeros, 8);

countLeadingZerosPartial(value, zeros, 4);

countLeadingZerosPartial(value, zeros, 2);

countLeadingZerosPartial(value, zeros, 1);

return zeros;

}

ARMThumbImmediate()

: m_type(TypeInvalid)

{

m_value.asInt = 0;

}

ARMThumbImmediate(ThumbImmediateType type, ThumbImmediateValue value)

: m_type(type)

, m_value(value)

{

}

ARMThumbImmediate(ThumbImmediateType type, uint16_t value)

: m_type(TypeUInt16)

{

// Make sure this constructor is only reached with type TypeUInt16;

// this extra parameter makes the code a little clearer by making it

// explicit at call sites which type is being constructed

ASSERT_UNUSED(type, type == TypeUInt16);

m_value.asInt = value;

}

public:

static ARMThumbImmediate makeEncodedImm(uint32_t value)

{

ThumbImmediateValue encoding;

encoding.asInt = 0;

// okay, these are easy.

if (value < 256) {

encoding.immediate = value;

encoding.pattern = 0;

return ARMThumbImmediate(TypeEncoded, encoding);

}

int32_t leadingZeros = countLeadingZeros(value);

// if there were 24 or more leading zeros, then we'd have hit the (value < 256) case.

ASSERT(leadingZeros < 24);

// Given a number with bit fields Z:B:C, where count(Z)+count(B)+count(C) == 32,

// Z are the bits known zero, B is the 8-bit immediate, C are the bits to check for

// zero. count(B) == 8, so the count of bits to be checked is 24 - count(Z).

int32_t rightShiftAmount = 24 - leadingZeros;

if (value == ((value >> rightShiftAmount) << rightShiftAmount)) {

// Shift the value down to the low byte position. The assign to

// shiftValue7 drops the implicit top bit.

encoding.shiftValue7 = value >> rightShiftAmount;

// The endoded shift amount is the magnitude of a right rotate.

encoding.shiftAmount = 8 + leadingZeros;

return ARMThumbImmediate(TypeEncoded, encoding);

}

PatternBytes bytes;

bytes.asInt = value;

if ((bytes.byte0 == bytes.byte1) && (bytes.byte0 == bytes.byte2) && (bytes.byte0 == bytes.byte3)) {

encoding.immediate = bytes.byte0;

encoding.pattern = 3;

return ARMThumbImmediate(TypeEncoded, encoding);

}

if ((bytes.byte0 == bytes.byte2) && !(bytes.byte1 | bytes.byte3)) {

encoding.immediate = bytes.byte0;

encoding.pattern = 1;

return ARMThumbImmediate(TypeEncoded, encoding);

}

if ((bytes.byte1 == bytes.byte3) && !(bytes.byte0 | bytes.byte2)) {

encoding.immediate = bytes.byte1;

encoding.pattern = 2;

return ARMThumbImmediate(TypeEncoded, encoding);

}

return ARMThumbImmediate();

}

static ARMThumbImmediate makeUInt12(int32_t value)

{

return (!(value & 0xfffff000))

? ARMThumbImmediate(TypeUInt16, (uint16_t)value)

: ARMThumbImmediate();

}

static ARMThumbImmediate makeUInt12OrEncodedImm(int32_t value)

{

// If this is not a 12-bit unsigned it, try making an encoded immediate.

return (!(value & 0xfffff000))

? ARMThumbImmediate(TypeUInt16, (uint16_t)value)

: makeEncodedImm(value);

}

// The 'make' methods, above, return a !isValid() value if the argument

// cannot be represented as the requested type. This methods is called

// 'get' since the argument can always be represented.

static ARMThumbImmediate makeUInt16(uint16_t value)

{

return ARMThumbImmediate(TypeUInt16, value);

}

bool isValid()

{

return m_type != TypeInvalid;

}

uint16_t asUInt16() const { return m_value.asInt; }

// These methods rely on the format of encoded byte values.

bool isUInt3() { return !(m_value.asInt & 0xfff8); }

bool isUInt4() { return !(m_value.asInt & 0xfff0); }

bool isUInt5() { return !(m_value.asInt & 0xffe0); }

bool isUInt6() { return !(m_value.asInt & 0xffc0); }

bool isUInt7() { return !(m_value.asInt & 0xff80); }

bool isUInt8() { return !(m_value.asInt & 0xff00); }

bool isUInt9() { return (m_type == TypeUInt16) && !(m_value.asInt & 0xfe00); }

bool isUInt10() { return (m_type == TypeUInt16) && !(m_value.asInt & 0xfc00); }

bool isUInt12() { return (m_type == TypeUInt16) && !(m_value.asInt & 0xf000); }

bool isUInt16() { return m_type == TypeUInt16; }

uint8_t getUInt3() { ASSERT(isUInt3()); return m_value.asInt; }

uint8_t getUInt4() { ASSERT(isUInt4()); return m_value.asInt; }

uint8_t getUInt5() { ASSERT(isUInt5()); return m_value.asInt; }

uint8_t getUInt6() { ASSERT(isUInt6()); return m_value.asInt; }

uint8_t getUInt7() { ASSERT(isUInt7()); return m_value.asInt; }

uint8_t getUInt8() { ASSERT(isUInt8()); return m_value.asInt; }

uint16_t getUInt9() { ASSERT(isUInt9()); return m_value.asInt; }

uint16_t getUInt10() { ASSERT(isUInt10()); return m_value.asInt; }

uint16_t getUInt12() { ASSERT(isUInt12()); return m_value.asInt; }

uint16_t getUInt16() { ASSERT(isUInt16()); return m_value.asInt; }

bool isEncodedImm() { return m_type == TypeEncoded; }

private:

ThumbImmediateType m_type;

ThumbImmediateValue m_value;

};

typedef enum {

SRType_LSL,

SRType_LSR,

SRType_ASR,

SRType_ROR,

SRType_RRX = SRType_ROR

} ARMShiftType;

class ShiftTypeAndAmount {

friend class ARMv7Assembler;

public:

ShiftTypeAndAmount()

{

m_u.type = (ARMShiftType)0;

m_u.amount = 0;

}

ShiftTypeAndAmount(ARMShiftType type, unsigned amount)

{

m_u.type = type;

m_u.amount = amount & 31;

}

unsigned lo4() { return m_u.lo4; }

unsigned hi4() { return m_u.hi4; }

private:

union {

struct {

unsigned lo4 : 4;

unsigned hi4 : 4;

};

struct {

unsigned type : 2;

unsigned amount : 6;

};

} m_u;

};

class ARMv7Assembler {

public:

typedef ARMRegisters::RegisterID RegisterID;

typedef ARMRegisters::FPSingleRegisterID FPSingleRegisterID;

typedef ARMRegisters::FPDoubleRegisterID FPDoubleRegisterID;

typedef ARMRegisters::FPQuadRegisterID FPQuadRegisterID;

// (HS, LO, HI, LS) -> (AE, B, A, BE)

// (VS, VC) -> (O, NO)

typedef enum {

ConditionEQ,

ConditionNE,

ConditionHS, ConditionCS = ConditionHS,

ConditionLO, ConditionCC = ConditionLO,

ConditionMI,

ConditionPL,

ConditionVS,

ConditionVC,

ConditionHI,

ConditionLS,

ConditionGE,

ConditionLT,

ConditionGT,

ConditionLE,

ConditionAL,

ConditionInvalid

} Condition;

#define JUMP_ENUM_WITH_SIZE(index, value) (((value) << 3) | (index))

#define JUMP_ENUM_SIZE(jump) ((jump) >> 3)

enum JumpType { JumpFixed = JUMP_ENUM_WITH_SIZE(0, 0),

JumpNoCondition = JUMP_ENUM_WITH_SIZE(1, 5 * sizeof(uint16_t)),

JumpCondition = JUMP_ENUM_WITH_SIZE(2, 6 * sizeof(uint16_t)),

JumpNoConditionFixedSize = JUMP_ENUM_WITH_SIZE(3, 5 * sizeof(uint16_t)),

JumpConditionFixedSize = JUMP_ENUM_WITH_SIZE(4, 6 * sizeof(uint16_t))

};

enum JumpLinkType {

LinkInvalid = JUMP_ENUM_WITH_SIZE(0, 0),

LinkJumpT1 = JUMP_ENUM_WITH_SIZE(1, sizeof(uint16_t)),

LinkJumpT2 = JUMP_ENUM_WITH_SIZE(2, sizeof(uint16_t)),

LinkJumpT3 = JUMP_ENUM_WITH_SIZE(3, 2 * sizeof(uint16_t)),

LinkJumpT4 = JUMP_ENUM_WITH_SIZE(4, 2 * sizeof(uint16_t)),

LinkConditionalJumpT4 = JUMP_ENUM_WITH_SIZE(5, 3 * sizeof(uint16_t)),

LinkBX = JUMP_ENUM_WITH_SIZE(6, 5 * sizeof(uint16_t)),

LinkConditionalBX = JUMP_ENUM_WITH_SIZE(7, 6 * sizeof(uint16_t))

};

class LinkRecord {

public:

LinkRecord(intptr_t from, intptr_t to, JumpType type, Condition condition)

: m_from(from)

, m_to(to)

, m_type(type)

, m_linkType(LinkInvalid)

, m_condition(condition)

{

}

intptr_t from() const { return m_from; }

void setFrom(intptr_t from) { m_from = from; }

intptr_t to() const { return m_to; }

JumpType type() const { return m_type; }

JumpLinkType linkType() const { return m_linkType; }

void setLinkType(JumpLinkType linkType) { ASSERT(m_linkType == LinkInvalid); m_linkType = linkType; }

Condition condition() const { return m_condition; }

private:

intptr_t m_from : 31;

intptr_t m_to : 31;

JumpType m_type : 8;

JumpLinkType m_linkType : 8;

Condition m_condition : 16;

};

private:

// ARMv7, Appx-A.6.3

bool BadReg(RegisterID reg)

{

return (reg == ARMRegisters::sp) || (reg == ARMRegisters::pc);

}

uint32_t singleRegisterMask(FPSingleRegisterID rdNum, int highBitsShift, int lowBitShift)

{

uint32_t rdMask = (rdNum >> 1) << highBitsShift;

if (rdNum & 1)

rdMask |= 1 << lowBitShift;

return rdMask;

}

uint32_t doubleRegisterMask(FPDoubleRegisterID rdNum, int highBitShift, int lowBitsShift)

{

uint32_t rdMask = (rdNum & 0xf) << lowBitsShift;

if (rdNum & 16)

rdMask |= 1 << highBitShift;

return rdMask;

}

typedef enum {

OP_ADD_reg_T1 = 0x1800,

OP_SUB_reg_T1 = 0x1A00,

OP_ADD_imm_T1 = 0x1C00,

OP_SUB_imm_T1 = 0x1E00,

OP_MOV_imm_T1 = 0x2000,

OP_CMP_imm_T1 = 0x2800,

OP_ADD_imm_T2 = 0x3000,

OP_SUB_imm_T2 = 0x3800,

OP_AND_reg_T1 = 0x4000,

OP_EOR_reg_T1 = 0x4040,

OP_TST_reg_T1 = 0x4200,

OP_RSB_imm_T1 = 0x4240,

OP_CMP_reg_T1 = 0x4280,

OP_ORR_reg_T1 = 0x4300,

OP_MVN_reg_T1 = 0x43C0,

OP_ADD_reg_T2 = 0x4400,

OP_MOV_reg_T1 = 0x4600,

OP_BLX = 0x4700,

OP_BX = 0x4700,

OP_STR_reg_T1 = 0x5000,

OP_STRH_reg_T1 = 0x5200,

OP_STRB_reg_T1 = 0x5400,

OP_LDR_reg_T1 = 0x5800,

OP_LDRH_reg_T1 = 0x5A00,

OP_LDRB_reg_T1 = 0x5C00,

OP_STR_imm_T1 = 0x6000,

OP_LDR_imm_T1 = 0x6800,

OP_STRB_imm_T1 = 0x7000,

OP_LDRB_imm_T1 = 0x7800,

OP_STRH_imm_T1 = 0x8000,

OP_LDRH_imm_T1 = 0x8800,

OP_STR_imm_T2 = 0x9000,

OP_LDR_imm_T2 = 0x9800,

OP_ADD_SP_imm_T1 = 0xA800,

OP_ADD_SP_imm_T2 = 0xB000,

OP_SUB_SP_imm_T1 = 0xB080,

OP_BKPT = 0xBE00,

OP_IT = 0xBF00,

OP_NOP_T1 = 0xBF00,

} OpcodeID;

typedef enum {

OP_B_T1 = 0xD000,

OP_B_T2 = 0xE000,

OP_AND_reg_T2 = 0xEA00,

OP_TST_reg_T2 = 0xEA10,

OP_ORR_reg_T2 = 0xEA40,

OP_ORR_S_reg_T2 = 0xEA50,

OP_ASR_imm_T1 = 0xEA4F,

OP_LSL_imm_T1 = 0xEA4F,

OP_LSR_imm_T1 = 0xEA4F,

OP_ROR_imm_T1 = 0xEA4F,

OP_MVN_reg_T2 = 0xEA6F,

OP_EOR_reg_T2 = 0xEA80,

OP_ADD_reg_T3 = 0xEB00,

OP_ADD_S_reg_T3 = 0xEB10,

OP_SUB_reg_T2 = 0xEBA0,

OP_SUB_S_reg_T2 = 0xEBB0,

OP_CMP_reg_T2 = 0xEBB0,

OP_VMOV_CtoD = 0xEC00,

OP_VMOV_DtoC = 0xEC10,

OP_VSTR = 0xED00,

OP_VLDR = 0xED10,

OP_VMOV_CtoS = 0xEE00,

OP_VMOV_StoC = 0xEE10,

OP_VMUL_T2 = 0xEE20,

OP_VADD_T2 = 0xEE30,

OP_VSUB_T2 = 0xEE30,

OP_VDIV = 0xEE80,

OP_VABS_T2 = 0xEEB0,

OP_VCMP = 0xEEB0,

OP_VCVT_FPIVFP = 0xEEB0,

OP_VMOV_T2 = 0xEEB0,

OP_VMOV_IMM_T2 = 0xEEB0,

OP_VMRS = 0xEEB0,

OP_VSQRT_T1 = 0xEEB0,

OP_B_T3a = 0xF000,

OP_B_T4a = 0xF000,

OP_AND_imm_T1 = 0xF000,

OP_TST_imm = 0xF010,

OP_ORR_imm_T1 = 0xF040,

OP_MOV_imm_T2 = 0xF040,

OP_MVN_imm = 0xF060,

OP_EOR_imm_T1 = 0xF080,

OP_ADD_imm_T3 = 0xF100,

OP_ADD_S_imm_T3 = 0xF110,

OP_CMN_imm = 0xF110,

OP_ADC_imm = 0xF140,

OP_SUB_imm_T3 = 0xF1A0,

OP_SUB_S_imm_T3 = 0xF1B0,

OP_CMP_imm_T2 = 0xF1B0,

OP_RSB_imm_T2 = 0xF1C0,

OP_ADD_imm_T4 = 0xF200,

OP_MOV_imm_T3 = 0xF240,

OP_SUB_imm_T4 = 0xF2A0,

OP_MOVT = 0xF2C0,

OP_UBFX_T1 = 0xF3C0,

OP_NOP_T2a = 0xF3AF,

OP_STRB_imm_T3 = 0xF800,

OP_STRB_reg_T2 = 0xF800,

OP_LDRB_imm_T3 = 0xF810,

OP_LDRB_reg_T2 = 0xF810,

OP_STRH_imm_T3 = 0xF820,

OP_STRH_reg_T2 = 0xF820,

OP_LDRH_reg_T2 = 0xF830,

OP_LDRH_imm_T3 = 0xF830,

OP_STR_imm_T4 = 0xF840,

OP_STR_reg_T2 = 0xF840,

OP_LDR_imm_T4 = 0xF850,

OP_LDR_reg_T2 = 0xF850,

OP_STRB_imm_T2 = 0xF880,

OP_LDRB_imm_T2 = 0xF890,

OP_STRH_imm_T2 = 0xF8A0,

OP_LDRH_imm_T2 = 0xF8B0,

OP_STR_imm_T3 = 0xF8C0,

OP_LDR_imm_T3 = 0xF8D0,

OP_LSL_reg_T2 = 0xFA00,

OP_LSR_reg_T2 = 0xFA20,

OP_ASR_reg_T2 = 0xFA40,

OP_ROR_reg_T2 = 0xFA60,

OP_CLZ = 0xFAB0,

OP_SMULL_T1 = 0xFB80,

} OpcodeID1;

typedef enum {

OP_VADD_T2b = 0x0A00,

OP_VDIVb = 0x0A00,

OP_VLDRb = 0x0A00,

OP_VMOV_IMM_T2b = 0x0A00,

OP_VMOV_T2b = 0x0A40,

OP_VMUL_T2b = 0x0A00,

OP_VSTRb = 0x0A00,

OP_VMOV_StoCb = 0x0A10,

OP_VMOV_CtoSb = 0x0A10,

OP_VMOV_DtoCb = 0x0A10,

OP_VMOV_CtoDb = 0x0A10,

OP_VMRSb = 0x0A10,

OP_VABS_T2b = 0x0A40,

OP_VCMPb = 0x0A40,

OP_VCVT_FPIVFPb = 0x0A40,

OP_VSUB_T2b = 0x0A40,

OP_VSQRT_T1b = 0x0A40,

OP_NOP_T2b = 0x8000,

OP_B_T3b = 0x8000,

OP_B_T4b = 0x9000,

} OpcodeID2;

struct FourFours {

FourFours(unsigned f3, unsigned f2, unsigned f1, unsigned f0)

{

m_u.f0 = f0;

m_u.f1 = f1;

m_u.f2 = f2;

m_u.f3 = f3;

}

union {

unsigned value;

struct {

unsigned f0 : 4;

unsigned f1 : 4;

unsigned f2 : 4;

unsigned f3 : 4;

};

} m_u;

};

class ARMInstructionFormatter;

// false means else!

bool ifThenElseConditionBit(Condition condition, bool isIf)

{

return isIf ? (condition & 1) : !(condition & 1);

}

uint8_t ifThenElse(Condition condition, bool inst2if, bool inst3if, bool inst4if)

{

int mask = (ifThenElseConditionBit(condition, inst2if) << 3)

| (ifThenElseConditionBit(condition, inst3if) << 2)

| (ifThenElseConditionBit(condition, inst4if) << 1)

| 1;

ASSERT((condition != ConditionAL) || !(mask & (mask - 1)));

return (condition << 4) | mask;

}

uint8_t ifThenElse(Condition condition, bool inst2if, bool inst3if)

{

int mask = (ifThenElseConditionBit(condition, inst2if) << 3)

| (ifThenElseConditionBit(condition, inst3if) << 2)

| 2;

ASSERT((condition != ConditionAL) || !(mask & (mask - 1)));

return (condition << 4) | mask;

}

uint8_t ifThenElse(Condition condition, bool inst2if)

{

int mask = (ifThenElseConditionBit(condition, inst2if) << 3)

| 4;

ASSERT((condition != ConditionAL) || !(mask & (mask - 1)));

return (condition << 4) | mask;

}

uint8_t ifThenElse(Condition condition)

{

int mask = 8;

return (condition << 4) | mask;

}

public:

void adc(RegisterID rd, RegisterID rn, ARMThumbImmediate imm)

{

// Rd can only be SP if Rn is also SP.

ASSERT((rd != ARMRegisters::sp) || (rn == ARMRegisters::sp));

ASSERT(rd != ARMRegisters::pc);

ASSERT(rn != ARMRegisters::pc);

ASSERT(imm.isEncodedImm());

m_formatter.twoWordOp5i6Imm4Reg4EncodedImm(OP_ADC_imm, rn, rd, imm);

}

void add(RegisterID rd, RegisterID rn, ARMThumbImmediate imm)

{

// Rd can only be SP if Rn is also SP.

ASSERT((rd != ARMRegisters::sp) || (rn == ARMRegisters::sp));

ASSERT(rd != ARMRegisters::pc);

ASSERT(rn != ARMRegisters::pc);

ASSERT(imm.isValid());

if (rn == ARMRegisters::sp) {

if (!(rd & 8) && imm.isUInt10()) {

m_formatter.oneWordOp5Reg3Imm8(OP_ADD_SP_imm_T1, rd, static_cast<uint8_t>(imm.getUInt10() >> 2));

return;

} else if ((rd == ARMRegisters::sp) && imm.isUInt9()) {

m_formatter.oneWordOp9Imm7(OP_ADD_SP_imm_T2, static_cast<uint8_t>(imm.getUInt9() >> 2));

return;

}

} else if (!((rd | rn) & 8)) {

if (imm.isUInt3()) {

m_formatter.oneWordOp7Reg3Reg3Reg3(OP_ADD_imm_T1, (RegisterID)imm.getUInt3(), rn, rd);

return;

} else if ((rd == rn) && imm.isUInt8()) {

m_formatter.oneWordOp5Reg3Imm8(OP_ADD_imm_T2, rd, imm.getUInt8());

return;

}

}

if (imm.isEncodedImm())

m_formatter.twoWordOp5i6Imm4Reg4EncodedImm(OP_ADD_imm_T3, rn, rd, imm);

else {

ASSERT(imm.isUInt12());

m_formatter.twoWordOp5i6Imm4Reg4EncodedImm(OP_ADD_imm_T4, rn, rd, imm);

}

}

ALWAYS_INLINE void add(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift)

{

ASSERT((rd != ARMRegisters::sp) || (rn == ARMRegisters::sp));

ASSERT(rd != ARMRegisters::pc);

ASSERT(rn != ARMRegisters::pc);

ASSERT(!BadReg(rm));

m_formatter.twoWordOp12Reg4FourFours(OP_ADD_reg_T3, rn, FourFours(shift.hi4(), rd, shift.lo4(), rm));

}

// NOTE: In an IT block, add doesn't modify the flags register.

ALWAYS_INLINE void add(RegisterID rd, RegisterID rn, RegisterID rm)

{

if (rd == rn)

m_formatter.oneWordOp8RegReg143(OP_ADD_reg_T2, rm, rd);

else if (rd == rm)

m_formatter.oneWordOp8RegReg143(OP_ADD_reg_T2, rn, rd);

else if (!((rd | rn | rm) & 8))

m_formatter.oneWordOp7Reg3Reg3Reg3(OP_ADD_reg_T1, rm, rn, rd);

else

add(rd, rn, rm, ShiftTypeAndAmount());

}

// Not allowed in an IT (if then) block.

ALWAYS_INLINE void add_S(RegisterID rd, RegisterID rn, ARMThumbImmediate imm)

{

// Rd can only be SP if Rn is also SP.

ASSERT((rd != ARMRegisters::sp) || (rn == ARMRegisters::sp));

ASSERT(rd != ARMRegisters::pc);

ASSERT(rn != ARMRegisters::pc);

ASSERT(imm.isEncodedImm());

if (!((rd | rn) & 8)) {

if (imm.isUInt3()) {

m_formatter.oneWordOp7Reg3Reg3Reg3(OP_ADD_imm_T1, (RegisterID)imm.getUInt3(), rn, rd);

return;

} else if ((rd == rn) && imm.isUInt8()) {

m_formatter.oneWordOp5Reg3Imm8(OP_ADD_imm_T2, rd, imm.getUInt8());

return;

}

}

m_formatter.twoWordOp5i6Imm4Reg4EncodedImm(OP_ADD_S_imm_T3, rn, rd, imm);

}

// Not allowed in an IT (if then) block?

ALWAYS_INLINE void add_S(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift)

{

ASSERT((rd != ARMRegisters::sp) || (rn == ARMRegisters::sp));

ASSERT(rd != ARMRegisters::pc);

ASSERT(rn != ARMRegisters::pc);

ASSERT(!BadReg(rm));

m_formatter.twoWordOp12Reg4FourFours(OP_ADD_S_reg_T3, rn, FourFours(shift.hi4(), rd, shift.lo4(), rm));

}

// Not allowed in an IT (if then) block.

ALWAYS_INLINE void add_S(RegisterID rd, RegisterID rn, RegisterID rm)

{

if (!((rd | rn | rm) & 8))

m_formatter.oneWordOp7Reg3Reg3Reg3(OP_ADD_reg_T1, rm, rn, rd);

else

add_S(rd, rn, rm, ShiftTypeAndAmount());

}

ALWAYS_INLINE void ARM_and(RegisterID rd, RegisterID rn, ARMThumbImmediate imm)

{

ASSERT(!BadReg(rd));

ASSERT(!BadReg(rn));

ASSERT(imm.isEncodedImm());

m_formatter.twoWordOp5i6Imm4Reg4EncodedImm(OP_AND_imm_T1, rn, rd, imm);

}

ALWAYS_INLINE void ARM_and(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift)

{

ASSERT(!BadReg(rd));

ASSERT(!BadReg(rn));

ASSERT(!BadReg(rm));

m_formatter.twoWordOp12Reg4FourFours(OP_AND_reg_T2, rn, FourFours(shift.hi4(), rd, shift.lo4(), rm));

}

ALWAYS_INLINE void ARM_and(RegisterID rd, RegisterID rn, RegisterID rm)

{

if ((rd == rn) && !((rd | rm) & 8))

m_formatter.oneWordOp10Reg3Reg3(OP_AND_reg_T1, rm, rd);

else if ((rd == rm) && !((rd | rn) & 8))

m_formatter.oneWordOp10Reg3Reg3(OP_AND_reg_T1, rn, rd);

else

ARM_and(rd, rn, rm, ShiftTypeAndAmount());

}

ALWAYS_INLINE void asr(RegisterID rd, RegisterID rm, int32_t shiftAmount)

{

ASSERT(!BadReg(rd));

ASSERT(!BadReg(rm));

ShiftTypeAndAmount shift(SRType_ASR, shiftAmount);

m_formatter.twoWordOp16FourFours(OP_ASR_imm_T1, FourFours(shift.hi4(), rd, shift.lo4(), rm));

}

ALWAYS_INLINE void asr(RegisterID rd, RegisterID rn, RegisterID rm)

{

ASSERT(!BadReg(rd));

ASSERT(!BadReg(rn));

ASSERT(!BadReg(rm));

m_formatter.twoWordOp12Reg4FourFours(OP_ASR_reg_T2, rn, FourFours(0xf, rd, 0, rm));

}

// Only allowed in IT (if then) block if last instruction.

ALWAYS_INLINE AssemblerLabel b()

{

m_formatter.twoWordOp16Op16(OP_B_T4a, OP_B_T4b);

return m_formatter.label();

}

// Only allowed in IT (if then) block if last instruction.

ALWAYS_INLINE AssemblerLabel blx(RegisterID rm)

{

ASSERT(rm != ARMRegisters::pc);

m_formatter.oneWordOp8RegReg143(OP_BLX, rm, (RegisterID)8);

return m_formatter.label();

}

// Only allowed in IT (if then) block if last instruction.

ALWAYS_INLINE AssemblerLabel bx(RegisterID rm)

{

m_formatter.oneWordOp8RegReg143(OP_BX, rm, (RegisterID)0);

return m_formatter.label();

}

void bkpt(uint8_t imm = 0)

{

m_formatter.oneWordOp8Imm8(OP_BKPT, imm);

}

ALWAYS_INLINE void clz(RegisterID rd, RegisterID rm)

{

ASSERT(!BadReg(rd));

ASSERT(!BadReg(rm));

m_formatter.twoWordOp12Reg4FourFours(OP_CLZ, rm, FourFours(0xf, rd, 8, rm));

}

ALWAYS_INLINE void cmn(RegisterID rn, ARMThumbImmediate imm)

{

ASSERT(rn != ARMRegisters::pc);

ASSERT(imm.isEncodedImm());

m_formatter.twoWordOp5i6Imm4Reg4EncodedImm(OP_CMN_imm, rn, (RegisterID)0xf, imm);

}

ALWAYS_INLINE void cmp(RegisterID rn, ARMThumbImmediate imm)

{

ASSERT(rn != ARMRegisters::pc);

ASSERT(imm.isEncodedImm());

if (!(rn & 8) && imm.isUInt8())

m_formatter.oneWordOp5Reg3Imm8(OP_CMP_imm_T1, rn, imm.getUInt8());

else

m_formatter.twoWordOp5i6Imm4Reg4EncodedImm(OP_CMP_imm_T2, rn, (RegisterID)0xf, imm);

}

ALWAYS_INLINE void cmp(RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift)

{

ASSERT(rn != ARMRegisters::pc);

ASSERT(!BadReg(rm));

m_formatter.twoWordOp12Reg4FourFours(OP_CMP_reg_T2, rn, FourFours(shift.hi4(), 0xf, shift.lo4(), rm));

}

ALWAYS_INLINE void cmp(RegisterID rn, RegisterID rm)

{

if ((rn | rm) & 8)

cmp(rn, rm, ShiftTypeAndAmount());

else

m_formatter.oneWordOp10Reg3Reg3(OP_CMP_reg_T1, rm, rn);

}

// xor is not spelled with an 'e'. :-(

ALWAYS_INLINE void eor(RegisterID rd, RegisterID rn, ARMThumbImmediate imm)

{

ASSERT(!BadReg(rd));

ASSERT(!BadReg(rn));

ASSERT(imm.isEncodedImm());

m_formatter.twoWordOp5i6Imm4Reg4EncodedImm(OP_EOR_imm_T1, rn, rd, imm);

}

// xor is not spelled with an 'e'. :-(

ALWAYS_INLINE void eor(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift)

{

ASSERT(!BadReg(rd));

ASSERT(!BadReg(rn));

ASSERT(!BadReg(rm));

m_formatter.twoWordOp12Reg4FourFours(OP_EOR_reg_T2, rn, FourFours(shift.hi4(), rd, shift.lo4(), rm));

}

// xor is not spelled with an 'e'. :-(

void eor(RegisterID rd, RegisterID rn, RegisterID rm)

{

if ((rd == rn) && !((rd | rm) & 8))

m_formatter.oneWordOp10Reg3Reg3(OP_EOR_reg_T1, rm, rd);

else if ((rd == rm) && !((rd | rn) & 8))

m_formatter.oneWordOp10Reg3Reg3(OP_EOR_reg_T1, rn, rd);

else

eor(rd, rn, rm, ShiftTypeAndAmount());

}

ALWAYS_INLINE void it(Condition cond)

{

m_formatter.oneWordOp8Imm8(OP_IT, ifThenElse(cond));

}

ALWAYS_INLINE void it(Condition cond, bool inst2if)

{

m_formatter.oneWordOp8Imm8(OP_IT, ifThenElse(cond, inst2if));

}

ALWAYS_INLINE void it(Condition cond, bool inst2if, bool inst3if)

{

m_formatter.oneWordOp8Imm8(OP_IT, ifThenElse(cond, inst2if, inst3if));

}

ALWAYS_INLINE void it(Condition cond, bool inst2if, bool inst3if, bool inst4if)

{

m_formatter.oneWordOp8Imm8(OP_IT, ifThenElse(cond, inst2if, inst3if, inst4if));

}

// rt == ARMRegisters::pc only allowed if last instruction in IT (if then) block.

ALWAYS_INLINE void ldr(RegisterID rt, RegisterID rn, ARMThumbImmediate imm)

{

ASSERT(rn != ARMRegisters::pc); // LDR (literal)

ASSERT(imm.isUInt12());

if (!((rt | rn) & 8) && imm.isUInt7())

m_formatter.oneWordOp5Imm5Reg3Reg3(OP_LDR_imm_T1, imm.getUInt7() >> 2, rn, rt);

else if ((rn == ARMRegisters::sp) && !(rt & 8) && imm.isUInt10())

m_formatter.oneWordOp5Reg3Imm8(OP_LDR_imm_T2, rt, static_cast<uint8_t>(imm.getUInt10() >> 2));

else

m_formatter.twoWordOp12Reg4Reg4Imm12(OP_LDR_imm_T3, rn, rt, imm.getUInt12());

}

ALWAYS_INLINE void ldrCompact(RegisterID rt, RegisterID rn, ARMThumbImmediate imm)