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| 1 | +/*- |
| 2 | + * BSD LICENSE |
| 3 | + * |
| 4 | + * Copyright(c) 2010-2014 Intel Corporation. All rights reserved. |
| 5 | + * All rights reserved. |
| 6 | + * |
| 7 | + * Redistribution and use in source and binary forms, with or without |
| 8 | + * modification, are permitted provided that the following conditions |
| 9 | + * are met: |
| 10 | + * |
| 11 | + * * Redistributions of source code must retain the above copyright |
| 12 | + * notice, this list of conditions and the following disclaimer. |
| 13 | + * * Redistributions in binary form must reproduce the above copyright |
| 14 | + * notice, this list of conditions and the following disclaimer in |
| 15 | + * the documentation and/or other materials provided with the |
| 16 | + * distribution. |
| 17 | + * * Neither the name of Intel Corporation nor the names of its |
| 18 | + * contributors may be used to endorse or promote products derived |
| 19 | + * from this software without specific prior written permission. |
| 20 | + * |
| 21 | + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 22 | + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 23 | + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| 24 | + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| 25 | + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| 26 | + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| 27 | + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 28 | + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 29 | + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 30 | + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| 31 | + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 32 | + */ |
| 33 | + |
| 34 | +#ifndef _RTE_ATOMIC_H_ |
| 35 | +#define _RTE_ATOMIC_H_ |
| 36 | + |
| 37 | +#ifdef __cplusplus |
| 38 | +extern "C" { |
| 39 | +#endif |
| 40 | + |
| 41 | +#define MPLOCKED "lock ; " /**< Insert MP lock prefix. */ |
| 42 | + |
| 43 | +/** |
| 44 | + * Compiler barrier. |
| 45 | + * |
| 46 | + * Guarantees that operation reordering does not occur at compile time |
| 47 | + * for operations directly before and after the barrier. |
| 48 | + */ |
| 49 | +#define rte_compiler_barrier() do { \ |
| 50 | + asm volatile ("" : : : "memory"); \ |
| 51 | +} while(0) |
| 52 | + |
| 53 | +static inline int |
| 54 | +rte_atomic32_cmpset(volatile uint32_t *dst, uint32_t exp, uint32_t src) |
| 55 | +{ |
| 56 | + uint8_t res; |
| 57 | + |
| 58 | + asm volatile( |
| 59 | + MPLOCKED |
| 60 | + "cmpxchgl %[src], %[dst];" |
| 61 | + "sete %[res];" |
| 62 | + : [res] "=a" (res), /* output */ |
| 63 | + [dst] "=m" (*dst) |
| 64 | + : [src] "r" (src), /* input */ |
| 65 | + "a" (exp), |
| 66 | + "m" (*dst) |
| 67 | + : "memory"); /* no-clobber list */ |
| 68 | + return res; |
| 69 | +} |
| 70 | + |
| 71 | +#ifdef __cplusplus |
| 72 | +} |
| 73 | +#endif |
| 74 | + |
| 75 | +#endif /* _RTE_ATOMIC_H_ */ |
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