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Commits on Dec 31, 2025

• Bump difftest: auto topIO connection and refactor checker (#255)

  klin02

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Commits on Nov 13, 2025

• Bump DiffTest for TopIO and DiffPhyRegState (#242)

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  klin02

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  e315a27

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Commits on Nov 7, 2025

• fpga_diff: fix FpgaDiffTop generation and renaming (#241)

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  klin02

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  d223222

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Commits on Nov 4, 2025

• FPGA: Fix the makefile to adapt to the fpgadifftop (#240)

  xiaokamikami

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  c347b0a

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Commits on Nov 2, 2025

• Bump Chisel 7.3.0 (#239)

  poemonsense

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  0752c4e

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• Bump DiffTest for refactor SimTop (#238)

  poemonsense

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Commits on Oct 15, 2025

• Bump Chisel 7.1.1 (#237)

  poemonsense

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Commits on Sep 21, 2025

• top: enable all layers by default (#236)

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  poemonsense

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Commits on Sep 19, 2025

• Bump Chisel 7.0.0 (#235)

  poemonsense

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Commits on Sep 12, 2025

• Device: add 16550 UART on fpga (#234)

  xiaokamikami

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  130cd27

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• top: Add a difftop for the fpgadiff platform (#233)

  xiaokamikami

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  82fe870

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Commits on Sep 7, 2025

• Bump DiffTest (#232)

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  poemonsense

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Commits on Jul 24, 2025

• Bump Chisel 6.7.0 (#230)

  poemonsense

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Commits on Dec 29, 2024

• Settings: disable Debug logs by default (#218)

  poemonsense

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Commits on Nov 6, 2024

• CSR: mark misa as unwritable (#213)

  poemonsense

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  61923a1

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Commits on Aug 26, 2024

• Merge pull request #206 from zhangziqing/oscpu-master-wip

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  poemonsense

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Commits on Aug 24, 2024

• add CI test for generating verilog on FPGA

  zhangziqing

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  ecce4b9

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• Fix the bug with the `REAL_TOP` calculation

  zhangziqing

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  e79841e

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Commits on Aug 19, 2024

• Disable Log for PYNQ and Axu3cg by adding disable EnableDebug flag

  zhangziqing

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  0aa8f62

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Commits on Aug 16, 2024

• Disable the log option for FPGA

  zhangziqing

  committed
  fdb8ed8

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• fix the bug for FPGA: post-process of AXI port naming and vivado add RTL file routine in tcl script

  zhangziqing

  committed
  1f84789

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• fix the topfile name while using FPGA

  zhangziqing

  committed
  6aa17a7

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• Modified the TCL generated by vivado 2019.1, to support higher version of vivado

  zhangziqing

  committed
  dfd0858

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• Fix the bug of nutcoretrap while using FPGA

  zhangziqing

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  3530593

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Commits on Jul 16, 2024

• Bump Chisel 6.5.0 (#203)

  poemonsense

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Commits on Jul 1, 2024

• Bump Chisel 6.4.0 and Scala 2.13.14 (#202)

  poemonsense

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Commits on Jun 27, 2024

• Merge pull request #201 from OSCPU/fix-bpu-x-state

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  sashimi-yzh

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  ba8347d

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• BPU: fix X state in vcs

  sashimi-yzh

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Commits on May 20, 2024

• Makefile: use xs_assert_v2 to include filename info (#199)

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  poemonsense

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Commits on May 15, 2024

• CSR: make mstatus.fs writable for software FPU emulation (#196)

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  poemonsense

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Commits on May 14, 2024

• CSR: sstatus.fs should be read-only zero (#195)

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  poemonsense

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Commits on May 13, 2024

• CSR: fix the wmask of mstatus (#194)

  poemonsense

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Commits on May 6, 2024

• NutShellSim: use 2GB AXI4RAM (#193)

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  poemonsense

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Commits on Apr 28, 2024

• AXI4RAM: remove the synthesizable option (#192)

  poemonsense

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  1868d83

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• ALU: mask off bit[0] for jump target (#191)

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  poemonsense

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