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Commits on Sep 27, 2025

• Create 017. Vector reversal 1.v

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• Delete Verilog Language /Vectors/vector_reversal_1.v

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• Create 018. Replication_factor.v

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• Create vector_reversal_1.v

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Commits on Jan 14, 2025

• Create 016 . Vector Concatenation operator.v

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• Create 015 . Four-Input gates.v

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• Create 014 . Bitwise Operators.v

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• Create 013 . Vector part Select.v

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  7ecc815

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• Delete Verilog Language /Vectors/0.13 Vector part Select.v

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• Create 0.13 Vector part Select.v

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• Delete Vectors directory

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• Delete Basic directory

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• Delete Verilog Language /Vectors/temp

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• Add files via upload

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• Create temp

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• Delete Verilog Language /Basics/temp

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  ecea342

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• Delete Verilog Language /temp

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• Add files via upload

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• Create temp

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  bd76cea

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• Create temp

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• Delete Verilog Language/Basics directory

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  c87be37

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• Create temp

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  1d03ac2

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• Delete Verilog Language/Basics directory

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  9507384

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• Add files via upload

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  3d0865e

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• Create temp

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• Delete 012. Vectors in more detail.v

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• Delete 011. Vectors.v

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• Delete 010. 7458 Chip.v

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• Delete 009. Declaring Wires.v

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• Delete 008. Xnor_Gate.v

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• Delete 007. Nor_Gate.v

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• Delete 006. And_Gate.v

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• Delete 005. Inverter.v

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• Delete 004. Four Wires.v

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• Delete 003. Simple Wire.v

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