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torvaldstorvalds
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd: "The core framework has a handful of patches this time around, mostly due to the clk rate protection support added by Jerome Brunet. This feature will allow consumers to lock in a certain rate on the output of a clk so that things like audio playback don't hear pops when the clk frequency changes due to shared parent clks changing rates. Currently the clk API doesn't guarantee the rate of a clk stays at the rate you request after clk_set_rate() is called, so this new API will allow drivers to express that requirement. Beyond this, the core got some debugfs pretty printing patches and a couple minor non-critical fixes. Looking outside of the core framework diff we have some new driver additions and the removal of a legacy TI clk driver. Both of these hit high in the dirstat. Also, the removal of the asm-generic/clkdev.h file causes small one-liners in all the architecture Kbuild files. Overall, the driver diff seems to be the normal stuff that comes all the time to fix little problems here and there and to support new hardware. Summary: Core: - Clk rate protection - Symbolic clk flags in debugfs output - Clk registration enabled clks while doing bookkeeping updates New Drivers: - Spreadtrum SC9860 - HiSilicon hi3660 stub - Qualcomm A53 PLL, SPMI clkdiv, and MSM8916 APCS - Amlogic Meson-AXG - ASPEED BMC Removed Drivers: - TI OMAP 3xxx legacy clk (non-DT) support - asm*/clkdev.h got removed (not really a driver) Updates: - Renesas FDP1-0 module clock on R-Car M3-W - Renesas LVDS module clock on R-Car V3M - Misc fixes to pr_err() prints - Qualcomm MSM8916 audio fixes - Qualcomm IPQ8074 rounded out support for more peripherals - Qualcomm Alpha PLL variants - Divider code was using container_of() on bad pointers - Allwinner DE2 clks on H3 - Amlogic minor data fixes and dropping of CLK_IGNORE_UNUSED - Mediatek clk driver compile test support - AT91 PMC clk suspend/resume restoration support - PLL issues fixed on si5351 - Broadcom IProc PLL calculation updates - DVFS support for Armada mvebu CPU clks - Allwinner fixed post-divider support - TI clkctrl fixes and support for newer SoCs" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (125 commits) clk: aspeed: Handle inverse polarity of USB port 1 clock gate clk: aspeed: Fix return value check in aspeed_cc_init() clk: aspeed: Add reset controller clk: aspeed: Register gated clocks clk: aspeed: Add platform driver and register PLLs clk: aspeed: Register core clocks clk: Add clock driver for ASPEED BMC SoCs clk: mediatek: adjust dependency of reset.c to avoid unexpectedly being built clk: fix reentrancy of clk_enable() on UP systems clk: meson-axg: fix potential NULL dereference in axg_clkc_probe() clk: Simplify debugfs registration clk: Fix debugfs_create_*() usage clk: Show symbolic clock flags in debugfs clk: renesas: r8a7796: Add FDP clock clk: Move __clk_{get,put}() into private clk.h API clk: sunxi: Use CLK_IS_CRITICAL flag for critical clks clk: Improve flags doc for of_clk_detect_critical() arch: Remove clkdev.h asm-generic from Kbuild clk: sunxi-ng: a83t: Add M divider to TCON1 clock clk: Prepare to remove asm-generic/clkdev.h ...
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‎Documentation/devicetree/bindings/clock/hi3660-clock.txt‎

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@@ -13,12 +13,18 @@ Required Properties:
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- "hisilicon,hi3660-pmuctrl"
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- "hisilicon,hi3660-sctrl"
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- "hisilicon,hi3660-iomcu"
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- "hisilicon,hi3660-stub-clk"
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- reg: physical base address of the controller and length of memory mapped
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region.
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- #clock-cells: should be 1.
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Optional Properties:
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- mboxes: Phandle to the mailbox for sending message to MCU.
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(See: ../mailbox/hisilicon,hi3660-mailbox.txt for more info)
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Each clock is assigned an identifier and client nodes use this identifier
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to specify the clock which they consume.
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‎Documentation/devicetree/bindings/clock/qcom,a53pll.txt‎

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Qualcomm MSM8916 A53 PLL Binding
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--------------------------------
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The A53 PLL on MSM8916 platforms is the main CPU PLL used used for frequencies
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above 1GHz.
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Required properties :
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- compatible : Shall contain only one of the following:
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"qcom,msm8916-a53pll"
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- reg : shall contain base register location and length
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- #clock-cells : must be set to <0>
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Example:
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a53pll: clock@b016000 {
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compatible = "qcom,msm8916-a53pll";
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reg = <0xb016000 0x40>;
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#clock-cells = <0>;
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};
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‎Documentation/devicetree/bindings/clock/qcom,spmi-clkdiv.txt‎

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Qualcomm Technologies, Inc. SPMI PMIC clock divider (clkdiv)
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clkdiv configures the clock frequency of a set of outputs on the PMIC.
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These clocks are typically wired through alternate functions on
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gpio pins.
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=======================
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Properties
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=======================
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- compatible
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Usage: required
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Value type: <string>
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Definition: must be "qcom,spmi-clkdiv".
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- reg
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Usage: required
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Value type: <prop-encoded-array>
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Definition: base address of CLKDIV peripherals.
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- qcom,num-clkdivs
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Usage: required
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Value type: <u32>
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Definition: number of CLKDIV peripherals.
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- clocks:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: reference to the xo clock.
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- clock-names:
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Usage: required
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Value type: <stringlist>
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Definition: must be "xo".
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- #clock-cells:
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Usage: required
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Value type: <u32>
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Definition: shall contain 1.
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=======
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Example
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=======
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pm8998_clk_divs: clock-controller@5b00 {
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compatible = "qcom,spmi-clkdiv";
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reg = <0x5b00>;
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#clock-cells = <1>;
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qcom,num-clkdivs = <3>;
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clocks = <&xo_board>;
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clock-names = "xo";
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assigned-clocks = <&pm8998_clk_divs 1>,
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<&pm8998_clk_divs 2>,
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<&pm8998_clk_divs 3>;
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assigned-clock-rates = <9600000>,
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<9600000>,
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<9600000>;
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};

‎Documentation/devicetree/bindings/clock/qoriq-clock.txt‎

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2 hwaccel index (n in CLKCGnHWACSR)
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3 fman 0 for fm1, 1 for fm2
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4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4
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4=pll/5, 5=pll/6, 6=pll/7, 7=pll/8
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5 coreclk must be 0
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3. Example

‎Documentation/devicetree/bindings/clock/silabs,si5351.txt‎

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- silabs,multisynth-source: source pll A(0) or B(1) of corresponding multisynth
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divider.
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- silabs,pll-master: boolean, multisynth can change pll frequency.
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- silabs,pll-reset: boolean, clock output can reset its pll.
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- silabs,disable-state : clock output disable state, shall be
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0 = clock output is driven LOW when disabled
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1 = clock output is driven HIGH when disabled

‎Documentation/devicetree/bindings/clock/sprd.txt‎

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Spreadtrum Clock Binding
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------------------------
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Required properties:
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- compatible: should contain the following compatible strings:
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- "sprd,sc9860-pmu-gate"
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- "sprd,sc9860-pll"
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- "sprd,sc9860-ap-clk"
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- "sprd,sc9860-aon-prediv"
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- "sprd,sc9860-apahb-gate"
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- "sprd,sc9860-aon-gate"
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- "sprd,sc9860-aonsecure-clk"
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- "sprd,sc9860-agcp-gate"
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- "sprd,sc9860-gpu-clk"
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- "sprd,sc9860-vsp-clk"
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- "sprd,sc9860-vsp-gate"
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- "sprd,sc9860-cam-clk"
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- "sprd,sc9860-cam-gate"
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- "sprd,sc9860-disp-clk"
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- "sprd,sc9860-disp-gate"
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- "sprd,sc9860-apapb-gate"
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- #clock-cells: must be 1
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- clocks : Should be the input parent clock(s) phandle for the clock, this
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property here just simply shows which clock group the clocks'
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parents are in, since each clk node would represent many clocks
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which are defined in the driver. The detailed dependency
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relationship (i.e. how many parents and which are the parents)
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are implemented in driver code.
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Optional properties:
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- reg: Contain the registers base address and length. It must be configured
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only if no 'sprd,syscon' under the node.
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- sprd,syscon: phandle to the syscon which is in the same address area with
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the clock, and so we can get regmap for the clocks from the
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syscon device.
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Example:
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pmu_gate: pmu-gate {
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compatible = "sprd,sc9860-pmu-gate";
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sprd,syscon = <&pmu_regs>;
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clocks = <&ext_26m>;
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#clock-cells = <1>;
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};
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pll: pll {
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compatible = "sprd,sc9860-pll";
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sprd,syscon = <&ana_regs>;
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clocks = <&pmu_gate 0>;
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#clock-cells = <1>;
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};
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ap_clk: clock-controller@20000000 {
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compatible = "sprd,sc9860-ap-clk";
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reg = <0 0x20000000 0 0x400>;
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clocks = <&ext_26m>, <&pll 0>,
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<&pmu_gate 0>;
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#clock-cells = <1>;
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};

‎Documentation/devicetree/bindings/clock/sun8i-de2.txt‎

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Required properties :
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- compatible: must contain one of the following compatibles:
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- "allwinner,sun8i-a83t-de2-clk"
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- "allwinner,sun8i-h3-de2-clk"
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- "allwinner,sun8i-v3s-de2-clk"
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- "allwinner,sun50i-h5-de2-clk"
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- reg: Must contain the registers base address and length
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- clocks: phandle to the clocks feeding the display engine subsystem.
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Three are needed:
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- "mod": the display engine module clock
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- "mod": the display engine module clock (on A83T it's the DE PLL)
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- "bus": the bus clock for the whole display engine subsystem
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- clock-names: Must contain the clock names described just above
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- resets: phandle to the reset control for the display engine subsystem.
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Example:
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de2_clocks: clock@1000000 {
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compatible = "allwinner,sun8i-a83t-de2-clk";
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compatible = "allwinner,sun8i-h3-de2-clk";
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reg = <0x01000000 0x100000>;
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clocks = <&ccu CLK_BUS_DE>,
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<&ccu CLK_DE>;

‎arch/alpha/include/asm/Kbuild‎

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# SPDX-License-Identifier: GPL-2.0
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generic-y += clkdev.h
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generic-y += exec.h
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generic-y += export.h
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generic-y += fb.h

‎arch/arc/include/asm/Kbuild‎

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# SPDX-License-Identifier: GPL-2.0
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generic-y += bugs.h
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generic-y += clkdev.h
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generic-y += device.h
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generic-y += div64.h
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generic-y += emergency-restart.h

‎arch/arm/include/asm/Kbuild‎

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generic-y += clkdev.h
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generic-y += current.h
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generic-y += early_ioremap.h
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generic-y += emergency-restart.h

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