Thesis Score Explorer
Search:
Min Score:
Category:
All Categories
Per page:
100
300
1000
3000
Loading data...
#
Title
Year
Country
Best Category
Best Score
AMS co-simulation
Analog layout & auto
RF/mmWave EDA
Analog schematic cap
Circuit simulators
Hardware generators
RTL/HDL & HLS design
Micro-architecture
SoC & interconnect i
Spec-to-RTL / system
Clock-tree synthesis
Floorplanning & powe
Physical optimizatio
Place & route
GDS generation & tap
Flow automation & sc
DFM / lithography ch
Design rule checking
LVS & extraction (PE
Equivalence checking
Logic optimization &
Low-power synthesis
RTL-to-gates synthes
Technology mapping
DFT & ATPG
Yield & reliability
Power integrity (IR/
Power estimation & o
Timing (STA) & signa
Emulation & FPGA pro
Formal verification
Linting & CDC/RDC
Assertion/property v
Simulation & testben
Secure ISA, SoC & is
Formal security veri
Logic locking & prov
Fault injection & PU
Side-channel analysi
Education, platforms
Hardware/tool licens
Reusable open IP & r
Open standards & dat
Open instruction set
3D integration & chi
Novel devices & beyo
Silicon photonics
Device modeling & TC
Variability & aging
Analog IP & primitiv
Memory compilers (SR
Std-cells & I/O libr
PDK, design rules &
← Previous
Next →