Simon Sapin SimonSapin

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• https://exyr.org
• Joined on 2025-08-31

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riscv-qemu-demo

Rust 0 0

Demo of freestanding Rust compiled to RISC-V running in QEMU

Updated 2026-03-15 14:23:32 +01:00

nandsim

Rust 0 0

Minimalistic simulator for logic circuits made entirely out of NAND logic gates

Updated 2026-03-13 18:34:50 +01:00

rvr

Rust 0 0

Toy project implementing a simulated RISC-V CPU, in Rust.

Updated 2026-03-13 16:22:46 +01:00

factoqual

TypeScript 0 0

Interactive calculator for quality upcycling loops in Factorio

Updated 2026-02-15 17:39:03 +01:00

exyr.org

HTML 0 0

Source code for my personal website

Updated 2026-02-15 08:53:24 +01:00

roustic

Rust 0 0

Playing around with restic’s repository format

Updated 2026-01-19 23:13:07 +01:00

unrv32c Archived

Rust 0 0

(Mostly not implemented) Uncompress RISC-V “C” Standard Extension for Compressed Instructions

Updated 2026-01-08 08:30:37 +01:00

snippets

Python 0 0

Pieces of code that are not big enough to be worth their own repository

Updated 2026-01-07 15:31:13 +01:00

teensy-clock

Rust 0 0

A digital clock based on Teensy 3.2 and Rust

Updated 2025-09-02 11:07:18 +02:00

rust-on-bbc-microbit

Rust 0 0

Running Rust code on a BBC micro:bit micro-controller

Updated 2025-09-02 10:57:36 +02:00