Unoptimized Input & Optimized Output
Metrics on Power Savings, Timing, and Gate Count

VeriRL Optimizer

Inspiration

We’re ECE majors who ran into the same problem: Verilog is central to RTL design but hard to use as clean training data for model-driven optimizations.
Real RTL corpora are small and noisy, and QoR-preserving (quality-of-result) transforms are rare.
We built a lightweight, local-first optimizer to iterate on these transformations reliably and reproducibly.

What We Learned

Fast iteration needs pragmatism: quick regex passes + a small AST pass strike a good demo tradeoff.
Simple heuristics work: even rough signals can guide meaningful UI-driven iteration.
Compact proxy score: summarizes Verilog complexity and drives visual feedback.

Score = 4R + 3A + 6B + 0.5O + 1.0L

where

(R) = number of reg / wire / logic declarations
(A) = number of assign statements
(B) = number of always blocks
(O) = operator occurrences
(L) = non-empty lines

Fractional changes (Δ) in this score are converted into conservative “percent-like” signals shown as power and timing indicators in the UI.

How We Built It

Frontend: React + Vite, implementing a simple paste → submit → poll → export workflow.
Backend: FastAPI serving job endpoints, connected to a Python worker.
Worker Modes:
- ML-backed inference: optional, for real LLM optimization.
- Deterministic demo optimizer (MOCK_HF=1): combines regex rewrites, a small RHS AST simplifier, and safe alias propagation.

To maintain correctness, the optimizer explicitly avoids renaming module ports — redeclarations become assign statements to preserve interfaces.

Challenges

LLM integration brittleness: inference timeouts and syntax inconsistencies pushed us to create a deterministic fallback.
Balancing visibility vs. correctness: visible simplifications are valuable for demos, but we kept the rewrite set conservative and explicitly protected ports.
Next step: a full parser/AST pipeline using tree-sitter or pyverilog for robust production-grade optimization.

Built as a reproducible sandbox to explore Verilog transformation pipelines for model-driven RTL optimization.