RISCstar community - Latest posts https://forums.riscstar.com Latest posts Compiler generating breakpoint instructions for simple maths Interesting. I tried to understand the arm assembly code, especially what will happen ‘sdiv’ divide-by-zero. The pseudo code in Arm’s website actually saying the behavior of ‘sdiv’ devide-by-zero is undefined (aka. implementation dependent). GCC’s implementation, insertion of ‘ebreak’, unified the behavior, which is pretty good.

if ConditionPassed() then
    EncodingSpecificOperations();
    if SInt(R[m]) == 0 then
        if IntegerZeroDivideTrappingEnabled() then
            GenerateIntegerZeroDivide();
        else
            result = 0;
    else
        result = RoundTowardsZero(SInt(R[n]) / SInt(R[m]));
    R[d] = result<31:0>;

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https://forums.riscstar.com/t/compiler-generating-breakpoint-instructions-for-simple-maths/15#post_4 Fri, 28 Nov 2025 23:46:41 +0000 forums.riscstar.com-post-22
Compiler generating breakpoint instructions for simple maths Pretty much, yes. We actually have to switch to A64 assembler to see what the codegen looks like for older gcc versions since the (upstream) RISC-V support doesn’t go back that far.

So for A64 recent gcc compilers compile that fragment to:

f:
        cbz     w1, .L6
        clz     w1, w1
        sdiv    w0, w0, w1
        ret
.L6:
        brk #1000

Whilst gcc 6 does the divide-by-zero via a conditional select:

f:
        clz     w2, w1
        cmp     w1, 0
        csel    w1, w2, w1, ne
        sdiv    w0, w0, w1
        ret

x86-64 is similar to A64 but using a branch rather than a conditional select in gcc 6.

Finally, if you are curious, clang simply assumes it doesn’t need to worry about the undefined case (which it doesn’t, it is undefined) and removes the zero check entirely. That means it ends up dividing by whatever the clz (or equivalent) instruction returns on 0 (which varies depending on instruction set).

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https://forums.riscstar.com/t/compiler-generating-breakpoint-instructions-for-simple-maths/15#post_3 Fri, 28 Nov 2025 11:02:59 +0000 forums.riscstar.com-post-21
Compiler generating breakpoint instructions for simple maths what happens if you throw this code to gcc before 2017? will it generates a div/0 code? :wink:

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https://forums.riscstar.com/t/compiler-generating-breakpoint-instructions-for-simple-maths/15#post_2 Fri, 28 Nov 2025 10:21:31 +0000 forums.riscstar.com-post-20
Compiler generating breakpoint instructions for simple maths If you read this expecting a compiler bug then prepare to be disappointed! This is just an “I didn’t know the compiler did that” observation that I stumbled across today whilst handling an oops report. I thought it was interesting.

So…

If we hand the following C to the GNU C compiler (including the RISCstar toolchain) then it will generate breakpoint instructions (or “undefined” instructions on x86-64):

int f(int x, int y) {
    return x / (y ? __builtin_clz(y) : 0);
}

The ternary would normally be an inline function but has been fully expanded in the example above. It has been defensively coded to avoid calling __builtin_clz(0) (which is undefined). Sadly in our case the output is used as a divisor meaning that, although the ternary has a defined value, there is still a divide-by-zero if y is zero… and that is also undefined.

Compilers can do pretty much anything when there is undefined behaviour (including removing the zero check entirely) but gcc’s behaviour is interesting. It recognises there is no point in generating any real code to implement behaviour that is known to be undefined so it generates a breakpoint instead!

f:
        beq     a1,zero,.L7  # Branch to .L7 if argument 1 is zero
        clzw    a1,a1        # Count Leading Zeros in Word 
        divw    a0,a0,a1     # Divide Word
        ret
.L7:
        ebreak               # Breakpoint

Doing a little archaeology led me to discover that gcc has been doing this since gcc 7.1 was released in 2017. However I’ve never seen it before. Perhaps I just don’t write enough undefined behavior bugs!

Anyhow, if you actually do find this is interesting, this is the Compiler Explorer sandpit I used to examine things a little more:

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https://forums.riscstar.com/t/compiler-generating-breakpoint-instructions-for-simple-maths/15#post_1 Tue, 25 Nov 2025 14:49:59 +0000 forums.riscstar.com-post-19
RISCstar toolchain 15.2-r1 has been released Actually, I nearly forgot.

There is actually a “secret” here (so don’t tell anyone :wink: ). The RVA23U64 binaries are actually built for rv64gcv_zicond_zba_zbb_zbs. This is not quite as aggressive as RVA23 and there is real hardware that can run the binaries today.

To be extremely clear this was a convenience for testing rather than some clever plan. The default build settings will change once real RVA23 hardware becomes available so don’t expect to be able to run later versions of the RISCstar toolchain on non-RVA23 hardware. That’s why it’s not documented and will remain so.

Again however, its absolutely fine to take advantage of this information for tasks like benchmarking.

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https://forums.riscstar.com/t/riscstar-toolchain-15-2-r1-has-been-released/11#post_4 Fri, 21 Nov 2025 10:12:18 +0000 forums.riscstar.com-post-17
RISCstar toolchain 15.2-r1 has been released I hope the rest of https://riscstar.com/toolchain is also clear that we intend the toolchain for RISC-V to support only RVA23. It’s not supposed to be a secret!

Others are very welcome to disagree but I personally think RVA23 marks such an important shift in the ecosystem that it’s better to baseline on this than to have needlessly slow compilers when RVA23 hardware arrives. As you observed we ship a couple of older versions of the toolchain where the native builds target RV64GC. That is offered just in case people with pre-RVA23 hardware really need them for comparative benchmarking and so on..

Finally, just in case there is any doubt, the toolchain itself can build binaries for whatever profile you want. The bundled libraries for the Linux toolchains are built for RV64GC but, in most cases, you’ll be dynamically linking anyway so the libraries you get at runtime are whatever comes from the distro you are running on the target board.

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https://forums.riscstar.com/t/riscstar-toolchain-15-2-r1-has-been-released/11#post_3 Fri, 21 Nov 2025 09:52:14 +0000 forums.riscstar.com-post-16
RISCstar toolchain 15.2-r1 has been released I noticed in 15.2-r1 (October 2025) release, the native toolchain is for “For RISC-V (RVA23U64 and later) hosts“, however, the 15.1-rc1 (July 2025) it is for “For RISC-V (RV64GC and later) hosts“. I wonder is there any special notes which I (as a user) should be aware of. Given the fact that RVA23U64 board is not available yet, should I avoid using it?

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https://forums.riscstar.com/t/riscstar-toolchain-15-2-r1-has-been-released/11#post_2 Fri, 21 Nov 2025 09:05:56 +0000 forums.riscstar.com-post-15
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https://forums.riscstar.com/t/about-the-arm-chat-category/12#post_1 Mon, 17 Nov 2025 10:48:35 +0000 forums.riscstar.com-post-13
RISCstar toolchain 15.2-r1 has been released At the RISC-V Summit North America, RISCstar announced the release of the latest version of the RISCstar toolchain for RISC-V.

The toolchain is based around gcc 15.2 supported by binutils 2.45 and gdb 16.3. Depending on the toolchain edition you will also find linux 6.5 kernel headers, glibc 2.38, musl 1.2.5 and/or newlib 4.5.

Note that 15.2-r1 is the first release where the RISC-V hosted compilers require RVA23. Learn more about the RISCstar toolchain at the RISCstar blog.

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https://forums.riscstar.com/t/riscstar-toolchain-15-2-r1-has-been-released/11#post_1 Mon, 17 Nov 2025 10:22:24 +0000 forums.riscstar.com-post-12
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