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AndersonHsieh0330/README.md
  • 👋 Hi, I’m Anderson Hsieh
  • I'm a 4th-year Computer Engineering student at the University of Waterloo.
  • Started my tech journey from mobile software, to backend server development, I now focus on digital hardware and ASIC design. Check out my resume for more details!
  • I believe the best way to learn is through personal projects. My most recent one is the WF8 8-bit Microproessor, where I implemented hardware in Verilog to run programs written in my own custom ISA.
  • I am also currently in charge of the task/order management system for Bristle Co. Ltd, a wheel brush manufacturing company located in Taoyuan Taiwan. Check out Bristle under my Github profile -> Organizations for more!
  • My short-term goal is to explore analog circuit design and utilize Tiny Taypeout and Skywater130 pdk.
  • Looking for full-time opportunities in semiconductor fields, please feel free to reach out to me if opportunities come across.

[email protected]
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  1. WF8 WF8 Public

    My own 8 bit ISA + RTL implementation CPU for FPGA and ASIC!

    Verilog 2

  2. eeprom_reader eeprom_reader Public

    24 series eeprom interfacing using Spartan 7 FPGA

    Tcl

  3. bpsk_modem bpsk_modem Public

    The DSP portion of a final year capstone from University of Waterloo ECE 2025 students

    VHDL