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Concept ACK, of course, though to be honest I'm not sure there is much value to spending the time to run this for every PR and merge. RISC-V is not sufficiently different from the other architectures, and we don't have any RISC-V specific assembly code. If we're going to test on wildly different architectures I'd prefer a big-endian MIPS run or such (see #6466). |
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Makes sense, and the |
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