Arm64/SVE: JitStress/JitStressRegs fixes#102543
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kunalspathak merged 17 commits intodotnet:mainfrom May 22, 2024
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…s LOW_PREDICATE flag
…_LowMaskedOperation
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Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch |
if falseReg == embMaskOp2Reg, we simply generate:
```
sel z16.s, p7, z9.s, z10.s
mla z16.s, p7/m, z10.s, z11.s
```
Here `z10` holds `falseReg` and `embMaskOp2Reg`.
a74nh
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May 22, 2024
TIHan
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LGTM. Glad we are catching these.
steveharter
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May 28, 2024
* handle case for FMA where falseReg == embMaskOp1Reg
* workaround because predicateRegister/vectorRegister are same
* When intrinsic is wrapped in ConditionalSelect, make sure to check its LOW_PREDICATE flag
* Mark AddAcross with HW_Flag_LowMaskedOperation
* double check if ConditionalSelect's op2 is hwintrinsic
* Mark Max with HW_Flag_LowMaskedOperation
* Mark MaxAcross with HW_Flag_LowMaskedOperation
* Mark MinNumber/MaxNumber/MinNumberAcross/MaxNumberAcross with HW_Flag_LowMaskedOperation
* Mark Min/MinAcross with HW_Flag_LowMaskedOperation
* fix the workaround for predicate vs. vector register
* fix the predicate mask preference
* Introduce INS_SCALABLE_OPTS_PREDICATE_MERGE_MOV
* jit format
* revert change to csproj
* remove assert that can not happen for FMA
if falseReg == embMaskOp2Reg, we simply generate:
```
sel z16.s, p7, z9.s, z10.s
mla z16.s, p7/m, z10.s, z11.s
```
Here `z10` holds `falseReg` and `embMaskOp2Reg`.
* revert a condition added for workaround of predicate == vector register
* remove the extra comment
Ruihan-Yin
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to Ruihan-Yin/runtime
that referenced
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May 30, 2024
* handle case for FMA where falseReg == embMaskOp1Reg
* workaround because predicateRegister/vectorRegister are same
* When intrinsic is wrapped in ConditionalSelect, make sure to check its LOW_PREDICATE flag
* Mark AddAcross with HW_Flag_LowMaskedOperation
* double check if ConditionalSelect's op2 is hwintrinsic
* Mark Max with HW_Flag_LowMaskedOperation
* Mark MaxAcross with HW_Flag_LowMaskedOperation
* Mark MinNumber/MaxNumber/MinNumberAcross/MaxNumberAcross with HW_Flag_LowMaskedOperation
* Mark Min/MinAcross with HW_Flag_LowMaskedOperation
* fix the workaround for predicate vs. vector register
* fix the predicate mask preference
* Introduce INS_SCALABLE_OPTS_PREDICATE_MERGE_MOV
* jit format
* revert change to csproj
* remove assert that can not happen for FMA
if falseReg == embMaskOp2Reg, we simply generate:
```
sel z16.s, p7, z9.s, z10.s
mla z16.s, p7/m, z10.s, z11.s
```
Here `z10` holds `falseReg` and `embMaskOp2Reg`.
* revert a condition added for workaround of predicate == vector register
* remove the extra comment
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falseReg == embMaskOp1Regmovwhen used as alias forselbecause predicateRegister/vectorRegister are sameConditionalSelect, check the intrinsic flag if it needs low register maskHW_Flag_LowMaskedOperationThere are still some functional failures with JitStress/JitStressRegs, but wanted to send this out.