What you'll learn
- SystemC language fundamentals — modules, processes, signals, events
- TLM 2.0 transport interface — sockets, generic payload, timing
- Modeling platform IPs — timers, clocks, resets, interrupt controllers
- Register modeling patterns — status, control, interrupt registers
- Virtual platform integration — bus fabric, address maps, clock trees
- Debug and verification techniques for TLM models
#include <systemc.h>
#include <tlm.h>
class Timer : public sc_module,
public tlm::tlm_fw_transport_if<> {
public:
tlm::tlm_target_socket<> socket;
sc_out<bool> irq;
SC_CTOR(Timer) : socket("socket") {
socket.bind(*this);
SC_THREAD(tick_thread);
}
void b_transport(tlm::tlm_generic_payload&, sc_time&);
void tick_thread();
};
SystemC Foundations
Installing SystemC on Windows, Linux & macOS
Build SystemC 2.3.3 from source, set environment variables, and verify with a Hello World before writing any simulation code.
Simulation Phases — Elaboration, Initialization, Execution, Cleanup
What the kernel does before sc_start() is called, why every signal fires at delta 0, and how to correctly register ports and processes in each phase.
SC_MODULE — Ports, Processes, and Hierarchy Explained
The complete SC_MODULE reference: macro expansion, SC_CTOR, sc_in/sc_out ports, SC_METHOD vs SC_THREAD, sensitivity lists, and module hierarchy.
SystemC Data Types — sc_uint, sc_logic, sc_fixed Explained
When to use sc_int vs sc_bv vs sc_lv vs sc_fixed — bit operations, 4-value logic, fixed-point arithmetic, and performance trade-offs.
SC_THREAD vs SC_METHOD — The Real Difference
The most important design decision in any SystemC model. When to use each process type, the rules, and the mistakes that silently break your simulation.
sc_signal and the Evaluate-Update Mechanism
Why sc_signal reads always lag one delta cycle, how the evaluate-update loop works under the hood, and the traps that catch engineers every day.
Events and Sensitivity in SystemC
sc_event, static sensitivity, and dynamic sensitivity from the ground up — and why a missed event can silently deadlock your simulation.
Delta Cycles — What Happens Inside One Timestep
The invisible heartbeat of every SystemC simulation. Understand the evaluate-update loop and what SC_ZERO_TIME actually does to the scheduler.
sc_main Deep Dive — Simulation Entry Point
Everything in sc_main: elaboration, sc_start() variants, sc_stop(), VCD tracing, sc_report_handler error handling, and a production-ready template.
sc_clock — Period, Duty Cycle, and Clock-Driven Design
All sc_clock constructor parameters, posedge/negedge events, port binding, multiple clock domains, and VCD waveform tracing.
Evolution of Channels in SystemC
From sc_signal wires to TLM sockets — how SystemC channels evolved across abstraction levels and why the channel-interface-port triad is the backbone of all communication.
Port Binding in SystemC
sc_in, sc_out, sc_inout — how ports connect modules to channels. Direct binding, hierarchical forwarding, the four binding rules, and common binding errors explained.
sc_fifo in SystemC
Buffered communication between processes — blocking write/read, non-blocking nb_write/nb_read, FIFO depth, events, and sc_fifo_in/sc_fifo_out port binding.
SystemC Scheduler Internals
Process states, the runnable queue, cooperative multitasking, initialization phase, execution order guarantees, SC_THREAD vs SC_METHOD in the scheduler, and starvation.
sc_mutex and sc_semaphore
Shared resource synchronization — sc_mutex for mutual exclusion, sc_semaphore for counting access, deadlock pitfalls, and a two-master shared bus example.
TLM 2.0 Core Concepts
TLM Generic Payload & Transport Interface
Understanding tlm_generic_payload, blocking vs non-blocking transport, and the initiator-target communication pattern.
Initiator & Target Sockets
How TLM sockets work, binding rules, multi-passthrough sockets, and building your first memory target.
Timing Annotation & Quantum Keeper
Loosely-timed vs approximately-timed modeling, temporal decoupling, and the quantum keeper mechanism.
IP & Peripheral Modeling
Modeling a Timer IP
Build a timer with configurable prescaler, auto-reload, capture/compare channels, and interrupt generation.
Clock & Reset Controllers
Modeling clock generation, PLL configuration, clock gating, reset sequencing, and power domain management.
Interrupt Controllers & Aggregators
Modeling interrupt routing, priority encoding, masking, pending/clear registers, and cascaded interrupt lines.
Watchdog Timer
Building a watchdog with window mode, early warning interrupt, and system reset generation on timeout.
Register Modeling Patterns
Status, control, and data registers. Read/write behaviors, write-1-to-clear, reserved bits, and access restrictions.
Virtual Platform Integration
Bus Fabric & Address Decode
Connecting IPs to a bus, address map configuration, bus bridges, and multi-layer interconnects.
Clock Trees & Reset Domains
Modeling system-level clock distribution, reset propagation, and power-on sequences across the platform.
Debug & Verification
Simulation Log Analysis
Reading simulation output, tracing TLM transactions, identifying read/write failures, and common error patterns.
Common Pitfalls & Best Practices
Deadlocks, delta-cycle issues, incorrect sensitivity, payload reuse bugs, and how to avoid them.