Deep dives into AI agents for EDA, SystemC internals, ARM architecture, and the hardware-software boundary where real engineering happens — written by someone building this stuff at Synopsys R&D.
// Latest Posts
Everything that happens in sc_main: elaboration, sc_start() semantics, multiple simulation runs, sc_stop(), VCD tracing, sc_report_handler error handling, and a production-ready template.
read →A complete guide to sc_clock: period, duty cycle, start time, posedge/negedge events, connecting clocks to ports, multiple clock domains, and VCD waveform tracing.
read →Step-by-step guide to building SystemC 2.3.3 from source on all three platforms — cmake flags, lib-macosxarm on Apple Silicon, environment variables, a Hello World verify, and a portable CMakeLists.txt template.
read →What the kernel does before sc_start() is called, why every signal fires at delta 0, and how to correctly register ports, sensitivity lists, and processes in each phase.
read →Why sc_signal reads always lag one delta cycle, how the evaluate-update loop works under the hood, and the traps that catch engineers every day — posedge, single-writer, sc_buffer, and more.
read →The complete SC_MODULE reference: macro expansion, SC_CTOR vs SC_HAS_PROCESS, sc_in/sc_out ports, SC_METHOD vs SC_THREAD, sensitivity lists, module hierarchy, and a full clock-counter-testbench example.
read →When to use sc_int vs sc_bv vs sc_lv vs sc_fixed — bit operations, 4-value logic, fixed-point arithmetic, and performance trade-offs in one complete reference.
read →The invisible heartbeat of every SystemC simulation. Understand the evaluate-update loop, why sc_signal reads lag by one cycle, and what SC_ZERO_TIME actually does to the scheduler.
read →sc_event, static sensitivity, and dynamic sensitivity from the ground up. Understand how processes wake up — and why a missed event can silently deadlock your simulation.
read →// Explore
Cortex-A, R, M series & micro-architecture internals
Object models, pointers, volatile, storage classes
Real-time logging, firmware, IoT device programming
Threads, CPU affinity, RTOS task management
sc_module, TLM 2.0 sockets, virtual platforms & ESL design
LLM-powered agents for hardware verification, spec-to-test generation, and agentic EDA workflows.
// What I Offer
Core learning for ports, signals, clocks, and data types. Build correct SystemC models step-by-step after signup.
TLM, advanced channel concepts, SCV-style verification, platform composition, and production-grade workflow. Paid access placeholder.
// About
I write about the things that live beneath the abstractions — processor pipelines, memory hierarchies, compiler behaviors, and the hardware-software boundary where real engineering happens.
Right now I'm building LLM-powered agents at Synopsys R&D that automate hardware verification — and writing about what that actually looks like from the inside.
ErrBits is a place to debug assumptions and understand how machines truly work, one bit at a time.