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errbits.com — bash
$ cat /dev/mindset

Debug the Bits.
Master the Machine.

Deep dives into AI agents for EDA, SystemC internals, ARM architecture, and the hardware-software boundary where real engineering happens — written by someone building this stuff at Synopsys R&D.

AI Agents for EDA SystemC / TLM 2.0 ARM Cortex C / C++ Embedded Systems Virtual Prototyping RTOS Pointers & Memory

// Latest Posts

Recent Articles

sc_main Deep Dive — SystemC Simulation Entry Point

Everything that happens in sc_main: elaboration, sc_start() semantics, multiple simulation runs, sc_stop(), VCD tracing, sc_report_handler error handling, and a production-ready template.

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sc_clock in SystemC — Period, Duty Cycle, and Clock-Driven Design

A complete guide to sc_clock: period, duty cycle, start time, posedge/negedge events, connecting clocks to ports, multiple clock domains, and VCD waveform tracing.

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Installing SystemC on Windows, Linux, and macOS

Step-by-step guide to building SystemC 2.3.3 from source on all three platforms — cmake flags, lib-macosxarm on Apple Silicon, environment variables, a Hello World verify, and a portable CMakeLists.txt template.

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Simulation Phases in SystemC — Elaboration, Initialization, Execution, Cleanup

What the kernel does before sc_start() is called, why every signal fires at delta 0, and how to correctly register ports, sensitivity lists, and processes in each phase.

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sc_signal and the Evaluate-Update Mechanism

Why sc_signal reads always lag one delta cycle, how the evaluate-update loop works under the hood, and the traps that catch engineers every day — posedge, single-writer, sc_buffer, and more.

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SC_MODULE in SystemC — Ports, Processes, and Hierarchy Explained

The complete SC_MODULE reference: macro expansion, SC_CTOR vs SC_HAS_PROCESS, sc_in/sc_out ports, SC_METHOD vs SC_THREAD, sensitivity lists, module hierarchy, and a full clock-counter-testbench example.

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SystemC Data Types — sc_uint, sc_logic, sc_fixed Explained

When to use sc_int vs sc_bv vs sc_lv vs sc_fixed — bit operations, 4-value logic, fixed-point arithmetic, and performance trade-offs in one complete reference.

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Delta Cycles in SystemC — What Happens Inside One Timestep

The invisible heartbeat of every SystemC simulation. Understand the evaluate-update loop, why sc_signal reads lag by one cycle, and what SC_ZERO_TIME actually does to the scheduler.

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Events and Sensitivity in SystemC — How Processes Know When to Run

sc_event, static sensitivity, and dynamic sensitivity from the ground up. Understand how processes wake up — and why a missed event can silently deadlock your simulation.

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SC_THREAD vs SC_METHOD — The Real Difference

SC_THREAD and SC_METHOD are not just two ways to do the same thing — they model fundamentally different simulation behaviors. When to use each, the rules, and the mistakes that silently break your model.

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Evolution of Channels in SystemC

From sc_signal wires to TLM sockets — how SystemC channels evolved across abstraction levels, and why the channel-interface-port triad is the backbone of all communication.

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Introduction to ARM Architecture and Its Impact

From Cortex-A to Cortex-M — how ARM diversified into three major categories and revolutionized mobile and embedded computing.

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Understanding C++ Object Model: Virtual Table and Virtual Pointer

How vptr and vtbl work under the hood — plus techniques to minimize the number of virtual pointer (vptr) loads in performance-critical C++ code.

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How to Create a Thread and Execute It on a Specific CPU Core

Pin threads to cores for deterministic performance. A practical guide to CPU affinity in multi-core systems.

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Real Time Logging for Embedded Systems and IoT

Efficient logging strategies for resource-constrained environments where every byte and cycle counts.

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Difference Between Structure and Union

Memory layout, alignment, and when to choose one over the other in embedded firmware development.

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Constant Pointer, Pointer to Constant and Constant Pointer to Constant

Three easily confused pointer qualifiers demystified — with memory diagrams and real use cases in embedded firmware.

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Volatile in C and Compiler Optimization

Why volatile matters for hardware registers, ISRs, and multi-threaded access — and what the compiler really does without it.

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Storage Classes in C

auto, register, static, extern — what they actually do to linkage, lifetime, and scope in C programs.

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Double Pointer in C

Pointer-to-pointer mechanics, memory layout, and practical patterns — dynamic 2D arrays, function output parameters and more.

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Pointers in C

The complete foundation — address arithmetic, dereferencing, null pointers, and the mental model every C developer needs.

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// Explore

Core Topics

🦾

ARM Architecture

Cortex-A, R, M series & micro-architecture internals

⚙️

C / C++ Internals

Object models, pointers, volatile, storage classes

📟

Embedded Systems

Real-time logging, firmware, IoT device programming

🧵

Concurrency

Threads, CPU affinity, RTOS task management

🔌

SystemC Modelling

sc_module, TLM 2.0 sockets, virtual platforms & ESL design

🤖

AI Agents for EDA

LLM-powered agents for hardware verification, spec-to-test generation, and agentic EDA workflows.

// What I Offer

Courses

SystemC Basics (Free)

Core learning for ports, signals, clocks, and data types. Build correct SystemC models step-by-step after signup.

Ports Signals Clocked Processes Data Types

SystemC Advanced (Upgrade Coming Soon)

TLM, advanced channel concepts, SCV-style verification, platform composition, and production-grade workflow. Paid access placeholder.

TLM Channels Verification Upgrade Soon

// About

Hey, I'm Aditya.

I write about the things that live beneath the abstractions — processor pipelines, memory hierarchies, compiler behaviors, and the hardware-software boundary where real engineering happens.

Right now I'm building LLM-powered agents at Synopsys R&D that automate hardware verification — and writing about what that actually looks like from the inside.

ErrBits is a place to debug assumptions and understand how machines truly work, one bit at a time.

Aditya Gaurav
Aditya Gaurav Virtual Prototype  ·  Architecture / Algorithmic Modelling  ·  Hardware Refinement Synopsys Inc  ·  Noida, India View Profile
// who am i
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};

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    "AI Agents for EDA",
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    "C/C++ Internals"
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