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1. -AHB2APB-Bridge-IP-Core-Verification -AHB2APB-Bridge-IP-Core-Verification Public

   Jun 2025 - Jul 2025 The AHB to APB bridge is an AHB slave which works as an interface between the high speed AHB and the low-performance APB buses.

   Verilog 1

2. -Router-1x3-RTL-Design-and-Verification -Router-1x3-RTL-Design-and-Verification Public

   Router 1x3– RTL Design and Verification Router 1x3– RTL Design and Verification The router accepts data packets on a single 8-bit port and routes them to one of the three outputs

   SystemVerilog

3. -AND_Gate_Verification -AND_Gate_Verification Public

   AND_Gate_Verification Test Strategy • Random Testing: Generate randomized inputs to cover all scenarios. • Functional Coverage: (Optional enhancement) Track coverage of all input combinations. • Se…

   SystemVerilog

4. Verilog_FIFO Verilog_FIFO Public

   FIFO

   HTML

5. Adder Adder Public

   Adder vlsi project