This project contains two main .v (verilog) files using which the project runs:
- barrel_shift_16bit.v : Main Verilog Code
- tb_barrel_shift_16bit.v : Test-bench File
The final outputs are shown below:
- Console Output:
- gtkwave Output (tb_project.vcd):
| Name | Name | Last commit date | ||
|---|---|---|---|---|
This project contains two main .v (verilog) files using which the project runs:
The final outputs are shown below: