RFSoC RoCE Offload provides an example design using RoCEv2 RDMA to stream data from an FPGA to a PC.

This project aims to provide:

• an FPGA design to send data from a streaming interface over RoCEv2
• a PYNQ notebook to configure the FPGA core and perform a handshake with software
• a sample PC software capable of receiving and processing the data

All under a permissive, open-source license

This repository will be updated with working code soon.