|
| 1 | +/* |
| 2 | + * test spi functions |
| 3 | + */ |
| 4 | + |
| 5 | +#include "Arduino.h" |
| 6 | +#include "wiring_private.h" |
| 7 | + |
| 8 | + |
| 9 | +void pinMode_asm(uint8_t pin, uint8_t mode) |
| 10 | +{ |
| 11 | + (void) pin; // empty code to avoid warning |
| 12 | + (void) mode; |
| 13 | +__asm |
| 14 | + sub sp, #16 |
| 15 | +#if 1 |
| 16 | +; pinmode.c: 10: uint8_t bit = digitalPinToBitMask(pin); |
| 17 | + clrw x |
| 18 | + |
| 19 | + ld a,(0x03, sp) |
| 20 | + ld xl,a |
| 21 | + addw x, #_digital_pin_to_bit_mask_PGM+0 |
| 22 | + ld a, (x) ; bit |
| 23 | + ld yl,a ; yl = bit |
| 24 | + cpl a |
| 25 | + ld yh,a ; yh = ~bit |
| 26 | + |
| 27 | +; pinmode.c: 11: uint8_t port = digitalPinToPort(pin); |
| 28 | +;;hier addw x, #_digital_pin_to_bit_mask_PGM - _digital_pin_to_bit_mask_PGM |
| 29 | + ld a, (x) ; port |
| 30 | + jreq 00018$ |
| 31 | + |
| 32 | + sll a |
| 33 | + clrw x |
| 34 | + ld xl,a |
| 35 | + addw x, #_port_to_output_PGM+0 ; x = gpio |
| 36 | + |
| 37 | + ld a,(0x04,sp) ; a = mode, flags are set |
| 38 | +#else |
| 39 | +; pinmode.c: 10: uint8_t bit = digitalPinToBitMask(pin); |
| 40 | + ldw x, #_digital_pin_to_bit_mask_PGM+0 |
| 41 | + ld a, xl |
| 42 | + add a, (0x13, sp) |
| 43 | + rlwa x |
| 44 | + adc a, #0x00 |
| 45 | + ld xh, a |
| 46 | + ld a, (x) |
| 47 | + ld (0x04, sp), a ; bit := 4 |
| 48 | +; pinmode.c: 11: uint8_t port = digitalPinToPort(pin); |
| 49 | + ldw x, #_digital_pin_to_port_PGM+0 |
| 50 | + ld a, xl |
| 51 | + add a, (0x13, sp) |
| 52 | + rlwa x |
| 53 | + adc a, #0x00 |
| 54 | + ld xh, a |
| 55 | + ld a, (x) |
| 56 | + ld (0x03, sp), a |
| 57 | + ld a, (0x03, sp) |
| 58 | + ld (0x07, sp), a ; port := 7 |
| 59 | +; pinmode.c: 14: if (port == NOT_A_PIN) return; |
| 60 | + tnz (0x03, sp) |
| 61 | + jrne 00002$ |
| 62 | + jp 00018$ |
| 63 | +00002$: |
| 64 | +; pinmode.c: 16: gpio = (GPIO_TypeDef *) portOutputRegister(port); |
| 65 | + ldw x, #_port_to_output_PGM+0 |
| 66 | + ldw (0x0e, sp), x |
| 67 | + ld a, (0x07, sp) |
| 68 | + ld xl, a |
| 69 | + ld a, #0x02 |
| 70 | + mul x, a |
| 71 | + addw x, (0x0e, sp) |
| 72 | + ldw x, (x) ; jetzt ist gpio in x |
| 73 | + |
| 74 | + ld a, (0x04, sp) ; bit |
| 75 | + ld yl,a ; yl = bit |
| 76 | + cpl a |
| 77 | + ld yh,a ; yh = ~bit |
| 78 | + ld a, (0x14, sp) ; a=mode, flags are set |
| 79 | +#endif |
| 80 | + |
| 81 | +; gpio->DDR: (2,x) (war an c,SP) |
| 82 | +; gpio->CR1: (3,x) (war an 8,SP) |
| 83 | +; gpio->CR2: (4,x) (war an 5,SP) |
| 84 | + |
| 85 | + sim |
| 86 | +; pinmode.c: 18: if (mode == INPUT) { |
| 87 | + jrne 00016$ |
| 88 | +; pinmode.c: 20: gpio->CR2 &= ~bit; // first: deactivate interrupt |
| 89 | + ld a,yh |
| 90 | + and a,(4,x) |
| 91 | + ld (4,x),a |
| 92 | +; pinmode.c: 21: gpio->CR1 &= ~bit; // release top side |
| 93 | + ld a,yh |
| 94 | + and a,(3,x) |
| 95 | + ld (3,x),a |
| 96 | +; pinmode.c: 22: gpio->DDR &= ~bit; // now set direction |
| 97 | + ld a,yh |
| 98 | + and a,(2,x) |
| 99 | + jp 00022$ |
| 100 | + |
| 101 | +00016$: |
| 102 | +; pinmode.c: 24: } else if (mode == INPUT_PULLUP) { |
| 103 | + cp a, #0x02 |
| 104 | + jrne 00013$ |
| 105 | +; pinmode.c: 26: gpio->CR2 &= ~bit; // first: deactivate interrupt |
| 106 | + ld a,yh |
| 107 | + and a,(4,x) |
| 108 | + ld (4,x),a |
| 109 | +; pinmode.c: 27: gpio->DDR &= ~bit; // set direction before |
| 110 | + ld a,yh |
| 111 | +and a,(2,x) |
| 112 | + ld (2,x),a |
| 113 | +; pinmode.c: 28: gpio->CR1 |= bit; // activating the pull up |
| 114 | + ld a,yl |
| 115 | + or a,(3,x) |
| 116 | + ld (3,x),a |
| 117 | + jp 00018$ |
| 118 | + |
| 119 | +00013$: |
| 120 | +; pinmode.c: 30: } else if (mode == OUTPUT_FAST) {// output push-pull, fast |
| 121 | + cp a, #0x05 |
| 122 | + jrne 00010$ |
| 123 | +; pinmode.c: 32: gpio->CR1 |= bit; |
| 124 | + ld a,yl |
| 125 | + or a,(3,x) |
| 126 | + jra 00020$ |
| 127 | +; pinmode.c: 39: gpio->DDR |= bit; // direction before setting CR2 to |
| 128 | +; pinmode.c: 40: gpio->CR2 |= bit; // avoid accidental interrupt |
| 129 | +00010$: |
| 130 | +; pinmode.c: 36: } else if (mode == OUTPUT_OD_FAST) { // output open drain, fast |
| 131 | + cp a, #0x07 |
| 132 | + jrne 00007$ |
| 133 | +; pinmode.c: 38: gpio->CR1 &= ~bit; |
| 134 | + ld a,yh |
| 135 | + and a,(3,x) |
| 136 | +00020$: ld (3,x),a |
| 137 | +; pinmode.c: 39: gpio->DDR |= bit; // direction before setting CR2 to |
| 138 | + ld a,yl |
| 139 | + or a,(2,x) |
| 140 | + ld (2,x),a |
| 141 | +; pinmode.c: 40: gpio->CR2 |= bit; // avoid accidental interrupt |
| 142 | + ld a,yl |
| 143 | + or a,(4,x) |
| 144 | + ld (4,x),a |
| 145 | + jra 00018$ |
| 146 | + |
| 147 | +00007$: |
| 148 | +; pinmode.c: 42: } else if (mode == OUTPUT_OD) { // output open drain, slow |
| 149 | + cp a, #0x03 |
| 150 | + jrne 00004$ |
| 151 | +; pinmode.c: 44: gpio->CR1 &= ~bit; |
| 152 | + ld a,yh |
| 153 | + and a,(3,x) |
| 154 | + jra 00021$ |
| 155 | +; pinmode.c: 45: gpio->CR2 &= ~bit; |
| 156 | +; pinmode.c: 46: gpio->DDR |= bit; |
| 157 | +00004$: |
| 158 | +; pinmode.c: 50: gpio->CR1 |= bit; |
| 159 | + ld a,yl |
| 160 | + or a,(3,x) |
| 161 | +00021$: ld (3,x),a |
| 162 | +; pinmode.c: 51: gpio->CR2 &= ~bit; |
| 163 | + ld a,yh |
| 164 | + and a,(4,x) |
| 165 | + ld (4,x),a |
| 166 | +; pinmode.c: 52: gpio->DDR |= bit; |
| 167 | + ld a,yl |
| 168 | + or a,(2,x) |
| 169 | +00022$: ld (2,x),a |
| 170 | +00018$: |
| 171 | + rim |
| 172 | + addw sp, #16 |
| 173 | +__endasm; |
| 174 | +} |
| 175 | + |
| 176 | + |
0 commit comments