This repository contains a synthesizable 64-bit RISC-V processor core implementing
the RV64I base integer instruction set along with the Zba address generation
extension.

• 5-stage pipelined microarchitecture (IF, ID, EX, MEM, WB)
• Separate instruction and data memories
• Supports standard RV64I arithmetic, logical, load/store, and branch instructions
• Implements Zba instructions: sh1add, sh2add, sh3add, and add.uw
• Designed and implemented in SystemVerilog

• Self-checking SystemVerilog testbench
• Runtime memory monitoring and register assertions
• Waveform generation for debug and analysis

• Compatible with RISC-V GNU toolchain
• Software-to-hardware flow documented in build_commands.md

• Design notes and architectural details available at docs/design_notes.md

• Full report with relavant explanations can be found here at docs/report.md

All core features verified through simulation with passing self-checking tests.

Note: AI tools were used exclusively for documentation writing and structuring. All design, implementation, and verification were performed manually