Course: EE 275 – Advanced Computer Architecture
Summary: 32-bit RISC-V ALU supporting ADD/SUB/MUL/logic ops in Verilog. Verified pipeline & control on Xilinx FPGA (Vivado). Achieved ~22% lower resource utilization vs baseline.

Verilog, FPGA, Vivado, RTL Design, ISA Simulation

• 32-bit ALU: add/sub/mul/and/or/xor/slt
• Basic pipeline & control verification
• Synthesis/implementation on Xilinx FPGA

1. Open the project in Vivado (version you used).
2. Set target board: <your board here>.
3. Run synthesis/implementation and generate bitstream.

• Resource utilization: ≈22% lower (LUT/FF/BRAM). See /reports.
• Timing met at <freq MHz>.