Welcome to the Sim43 repository! This project implements an 8-bit RISC microcontroller using Verilog. 🖥️🔧

• 8-bit RISC Architecture 🧠
• Custom Instruction Set 📜
• Single-Cycle Execution ⏱️
• General-Purpose Registers 📚
• ALU Operations ➕➖✖️➗
• Memory Interface 🗄️
• GPIO Support 🔌

This project was designed using Quartus Lite and simulated in ModelSim. To get started:

1. Clone the repository 📂

   git clone https://github.com/Sim43/Sim43-8-bit-RISC-Microcontroller-Verilog.git
   

2. Navigate to the project directory 📁

   cd Sim43-8-bit-RISC-Microcontroller-Verilog
   

3. Open the project in Quartus Lite 🛠️

4. Simulate the project using ModelSim 🧪

Ensure you have the following tools installed:

• Intel Quartus Prime Lite Edition 🎛️
• ModelSim Simulator 🖥️

1. Compile the Verilog files in Quartus Lite 📝
2. Run simulations in ModelSim to verify functionality ✔️
3. Optionally, synthesize the design for FPGA hardware 🏗️

Contributions are welcome! Please fork this repository and submit a pull request. For major changes, open an issue first to discuss what you would like to change. 📝

• Designed and tested using Quartus Lite and ModelSim. 🛠️
• Inspired by various open-source microcontroller projects. 💡
• Thanks to the Verilog and FPGA development communities for their support and resources. 🌐