This repository contains the final project for the university course Reti Logiche (Logic Networks), developed by a two-person team during the 2022/2023 academic year.

The goal of the project was to design, implement, and verify in VHDL a hardware component that receives a serial input stream, selects one of four output channels, reads a memory word, and stores the value so it can later be shown on the chosen output.

• Goal: build a synthesizable VHDL circuit for a final course assignment.
• Core behavior: read a serial configuration stream, fetch a byte from memory, and route it to the selected output.
• Outputs: four persistent 8-bit channels that keep their last assigned value until overwritten or reset.
• Implementation: structured around a FSM, shift registers, output registers, and a demultiplexer.
• Verification: supported by Vivado simulations and a dedicated set of testbenches.

• Serial input handling with bit-by-bit capture of the output selector and memory address.
• Persistent output registers that preserve the last valid memory value for each channel.
• Clean control flow managed by a dedicated finite state machine.
• Reusable datapath blocks that keep the design modular and easy to inspect.
• Complete test coverage across reset cases, address edge cases, overwrite behavior, and all four outputs.

• Documentation
• Main VHDL design
• Testbench collection
• Vivado project
• License

The circuit implements a small memory-routing system with the following external interface:

• one serial input for the output-channel selection and memory address bits
• four 8-bit outputs: Z0, Z1, Z2, Z3
• a DONE signal that marks the end of an operation
• a 16-bit memory address output
• memory enable and write-enable control signals

At a high level, the component:

1. reads two bits to select which output register must be updated
2. reads the memory address bit by bit
3. requests the value from memory
4. stores the returned byte in the selected output register
5. exposes the stored value on the chosen output when DONE is asserted

The design is split into a few reusable blocks:

• FSM: controls the full execution flow and drives the internal control signals.
• 2-bit shift register: stores the selected output channel.
• 16-bit address register: collects the memory address and expands it to the required width.
• DeMux: routes the returned memory byte to the correct output register.
• 4 output registers: keep the last value assigned to each output channel.

The top-level entity is implemented in project_reti_logiche.vhd, while the support blocks are stored in the same source directory.

The detailed design report is available in documentation/10710827_10742651.tex. It includes:

• the original project specification
• the complete FSM description
• the datapath rationale
• the register and demultiplexer design choices
• synthesis observations
• simulation strategy and test coverage

The repository includes several VHDL testbenches and simulation artifacts used to validate the design in Vivado. The test suite covers cases such as:

• empty address handling
• full-length address capture
• maximum address value
• updates on all four outputs
• output overwrite behavior
• reset behavior in different execution phases

Useful material can be found under testbenches/ and in the Vivado-generated simulation folders.

• datapath/ contains the original datapath sketch and related material
• documentation/ contains the full written report
• final/ contains the final Vivado project and generated implementation artifacts
• rl_project_2023/ contains the main Vivado project sources and simulation files
• testbenches/ contains the standalone VHDL testbenches and run notes

The easiest way to explore or simulate the design is to open one of the Vivado projects:

1. Start Xilinx Vivado.
2. Open final/final.xpr or rl_project_2023/rl_project_2023.xpr.
3. Inspect the source files in sources_1/new.
4. Run the available simulations from the Test Bench section.

If you only want to read the implementation, the main entry point is project_reti_logiche.vhd.

• Edoardo D'Alessio, student code 10710827
• Simone Deidier, student code 10742651

This repository is distributed under the terms of the GNU General Public License v3.0 (LICENSE).