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32-bit ALU UVM Verification

Professional Verification Environment using UVM, IMC, SimVision & verisium Debug

Build Status Coverage

Table of Contents

Overview

This project provides a complete UVM (Universal Verification Methodology) environment for a 32-bit ALU.
It ensures functional correctness, performance, and reliability using constrained-random stimulus, coverage analysis, and assertions.

Features

  • UVM Components: Driver, Monitor, Sequencer, Scoreboard, Functional coverage, Assertions
  • ALU Operations: Add, Subtract, AND, OR, XOR,Overflow detection
  • Verification Methodology: Constrained-random tests, Transaction-based sequences, Reference model comparison

Tools Used

  • IMC – Metrics & Coverage Collection
  • SimVision – Waveform viewing & simulation debug
  • Verisim Debug – Step-by-step RTL debugging
  • Synopsys VCS – RTL simulation engine

About

This repository contains a 32-bit Arithmetic Logic Unit (ALU) fully verified using a Universal Verification Methodology (UVM) environment written in SystemVerilog.

Topics

waveform-analysis rtl-design uvm-verification verisium-interactive

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