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1. cv32e40p cv32e40p Public

   Forked from openhwgroup/cv32e40p

   CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

   SystemVerilog

2. corev-llvm-project corev-llvm-project Public

   Forked from openhwgroup/corev-llvm-project

3. CoreDSL CoreDSL Public

   Forked from Minres/CoreDSL

   Xtext project to parse CoreDSL files

   Xtend

4. RISCV_ISA_CoreDSL RISCV_ISA_CoreDSL Public

   Forked from Minres/RISCV_ISA_CoreDSL

   CoreDSL descriptions of the RISC-V ISA

5. M2-ISA-R M2-ISA-R Public

   Forked from tum-ei-eda/M2-ISA-R

   CoreDSL2 Parser with backend to generate simulation code for the ETISS instruction set simulator

   Python

6. etiss_arch_riscv etiss_arch_riscv Public

   Forked from tum-ei-eda/etiss_arch_riscv

   RISC-V architecture models for ETISS