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chandanpalai/fpga_dac

 
 

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fpga_dac

Project which creates an analogic sine signal from of an architecture that involves FPGA. It were used a DDS core to generate the sine and SPI communication to control DAC conversor (AD5791 Analog Devices). To choose the sine frequency and the update frequency of a new data we developed a cpp application. The "documentation" folder has more details of the project, including datasheets, state machine and block diagram.

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Project which creates an analogic sine signal from an architecture that involves FPGA. It were used a DDS core to generate the sine and SPI communication to control DAC conversor (AD5791 Analog Devices). To choose the sine frequency and the update frequency of a new data we developed a cpp application. The "documentation" folder has more details…

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  • Verilog 57.1%
  • VHDL 39.0%
  • C++ 2.6%
  • Other 1.3%