Project which creates an analogic sine signal from of an architecture that involves FPGA. It were used a DDS core to generate the sine and SPI communication to control DAC conversor (AD5791 Analog Devices). To choose the sine frequency and the update frequency of a new data we developed a cpp application. The "documentation" folder has more details of the project, including datasheets, state machine and block diagram.
chandanpalai/fpga_dac
Folders and files
| Name | Name | Last commit date | ||
|---|---|---|---|---|
Repository files navigation
Releases
No releases published
Languages
- Verilog 57.1%
- VHDL 39.0%
- C++ 2.6%
- Other 1.3%