Update easyconfig LLVM-20.1.5-GCCcore-13.2.0.eb for RISC-V#22656
Update easyconfig LLVM-20.1.5-GCCcore-13.2.0.eb for RISC-V#22656Crivella merged 40 commits intoeasybuilders:developfrom
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Disabling offload altogether also disables offload for NVIDIA & AMD GPUs on RISC-V, though I'm not expecting that CUDA or ROCm work on RISC-V in the near future. So I consider this being okay. We should update the other LLVM ECs as well though, to be consistent. |
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These are the results using this PR:
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I do not think disabling the offload is the way to go, from the test you showed on easybuilders/easybuild-easyblocks#3676 (comment) i think it is already working but there is a bug in the test suite. We can either add an ignore pattern for those tests or as suggested in easybuilders/easybuild-easyblocks#3676 (comment) try to add a new patch / modify the existing one to get the proper target to be found. I would start by doing an ls inside |
OpenMP offloading is not supported in this version of LLVM for RISC-V. When doing OpenMP offload, LLVM assumes two things:
LLVM only supports this debug OpenMP offload on x86_64 and aarch64 (and maybe powerpc64le), but not for riscv64. |
…-jmorillo into LLVM
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@boegelbot please test @ jsc-zen3 |
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@julianmorillo I am fine with all the patches here, was wondering if there is also communication with upstream to make sure all the tests that you verified are unsupported for RISC-V are also being properly flagged upstream? |
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@Crivella: Request for testing this PR well received on jsczen3l1.int.jsc-zen3.fz-juelich.de PR test command '
Test results coming soon (I hope)... Details- notification for comment with ID 3117642399 processed Message to humans: this is just bookkeeping information for me, |
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Test report by @boegelbot |
Co-authored-by: Davide Grassano <[email protected]>
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See the suggested changes to apply the new patches only when we are on RISCV
Co-authored-by: Davide Grassano <[email protected]>
Co-authored-by: Davide Grassano <[email protected]>
Co-authored-by: Davide Grassano <[email protected]>
Co-authored-by: Davide Grassano <[email protected]>
Co-authored-by: Davide Grassano <[email protected]>
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@boegelbot please test @ jsc-zen3 |
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@Crivella: Request for testing this PR well received on jsczen3l1.int.jsc-zen3.fz-juelich.de PR test command '
Test results coming soon (I hope)... Details- notification for comment with ID 3140093605 processed Message to humans: this is just bookkeeping information for me, |
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Test report by @boegelbot |
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Going in, thanks @julianmorillo! |
@Crivella , I discussed some of the cases with one of the LLVM developers, and I have submitted the following PRs to the LLVM repo: |
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