This repository contains the design of an IP block for Merge Sort acceleration on FPGA for the FPGA101 PiA Course Project by Politecnico di Milano.

The repo contains three different folders for each architecture experimented, namely tree, row, hybrid, a pdf report describing the proceudre adopted and the results obtained and, lastly, a jupyter notebook to run the final designs on the PYNQ-Z2 FPGA and compare their performances with the SW algorithm implementation.