Smaller image and FPGA core

better terminal handling

simplification of the interpreter

simpler CPU

cleanup and optimize

Initial complete system

new indirect instructions

Added second store instruction

This instruction allows us to perform direct stores whilst the indirect flag is
on. We can perform direct loads when that flag is on by clearing the
accumulator and OR'ing the result in instead of using the load
instruction. It might be worth clearing the contents of the accumulator
on a store...

This commit slightly increases the size of the CPU, I would like to
shrink it again - perhaps by trying out different CPU instruction
ordering...

+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| Module             | Partition | Slices*       | Slice Reg     | LUTs          | LUTRAM        | BRAM/FIFO | DSP48A1 | BUFG  | BUFIO | BUFR  | DCM   | PLL_ADV   | Full Hierarchical Name       |
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| top/               |           | 0/100         | 0/231         | 0/261         | 0/4           | 0/5       | 0/0     | 1/1   | 0/0   | 0/0   | 0/0   | 0/0       | top                          |
| +cpu               |           | 25/25         | 54/54         | 72/72         | 4/4           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | 0/0       | top/cpu                      |
| +peripheral        |           | 20/75         | 49/177        | 56/189        | 0/0           | 1/5       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | 0/0       | top/peripheral               |
| ++bram             |           | 0/0           | 0/0           | 0/0           | 0/0           | 4/4       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | 0/0       | top/peripheral/bram          |
| ++uart             |           | 3/55          | 3/128         | 3/133         | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | 0/0       | top/peripheral/uart          |
| +++baud_rx         |           | 13/13         | 37/37         | 31/31         | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | 0/0       | top/peripheral/uart/baud_rx  |
| +++baud_tx         |           | 14/14         | 37/37         | 30/30         | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | 0/0       | top/peripheral/uart/baud_tx  |
| +++rx_0            |           | 14/14         | 27/27         | 41/41         | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | 0/0       | top/peripheral/uart/rx_0     |
| +++tx_0            |           | 11/11         | 24/24         | 28/28         | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | 0/0       | top/peripheral/uart/tx_0     |
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

Initial Working Version