CSE31L_32_BIT_PROCESSOR

Group Project to design a 32 bit processor using SystemVerilog

Name		Name	Last commit message	Last commit date
Latest commit History 72 Commits
32 Bit ALU		32 Bit ALU
Controller		Controller
Data Memory		Data Memory
FINAL SUBMISSION		FINAL SUBMISSION
Implementation Files		Implementation Files
Instruction Memory Block		Instruction Memory Block
Processor		Processor
Register Block		Register Block
README.md		README.md

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