Improve the descriptions of the HyperRAM-related switches

There are two switches and neither is exclusively HyperRAM-related.

One controls the clocking scheme and gives a more accurate
simulation of the USB device and/or HyperRAM controller as desired.

The second controls whether a SRAM model is used in place of the
HyperRAM controller; this may be used in simulation for a faster
simulation or in synthesis when targeting SonataXL which has no
HyperRAM.

Linker file indentation fix

Pre-release that includes CHERIoT debug module

Verilator unoptflat stop for rvfi_rd_addr

This is introduced upstream and mainly indicates that Verilator cannot
simulate this efficiently. Functionality is fine though.

Connect arduino shield pin 9 to correct PWM channel

Previously both pin 6 and 9 were connected to PWM channel 2

Enable SPI external loopback test between MB3 & MB4

Enables the SPI external loopback test by adding an external jumper
cable between pins MB3 and MB4 on the mikroBUS click header. Performs
appropriate pinmuxing if the SPI test is configured to run this test, so
that the test can pass.

Co-authored-by: Adrian Lees <[email protected]>

No default UART TX output to RS485

Added license lint

Enable CHERIoT Ibex ICache

v0.3 release