GitHub - mattstock/fpgalib: A common core of Verilog that can be used for multiple projects.

Name		Name	Last commit message	Last commit date
Latest commit History 330 Commits
altsource_probe		altsource_probe
bexkat1		bexkat1
bexkat2		bexkat2
cache		cache
debounce		debounce
edge_detect		edge_detect
intr_capturer		intr_capturer
mandelbrot		mandelbrot
qsys-presets		qsys-presets
sdram		sdram
spi		spi
templates/devplatforms		templates/devplatforms
uart		uart
vga-old		vga-old
vga		vga
.gitignore		.gitignore
bexkat1_hw.tcl		bexkat1_hw.tcl
bus_stub.sv		bus_stub.sv
bus_term.sv		bus_term.sv
dualfifo.sv		dualfifo.sv
dualram.sv		dualram.sv
dualram2clock.sv		dualram2clock.sv
dualrom.sv		dualrom.sv
fan_ctrl.v		fan_ctrl.v
fan_ctrl_hw.tcl		fan_ctrl_hw.tcl
fifo.sv		fifo.sv
ghrd_reset.tcl		ghrd_reset.tcl
ghrd_sc_script.tcl		ghrd_sc_script.tcl
hexdisp.v		hexdisp.v
interrupt_encoder.sv		interrupt_encoder.sv
intr_capturer_hw.tcl		intr_capturer_hw.tcl
led_matrix.sv		led_matrix.sv
mandelbrot_hw.tcl		mandelbrot_hw.tcl
mmu.v		mmu.v
paneldigit.sv		paneldigit.sv
paneldisp.sv		paneldisp.sv
ps2_kbd.sv		ps2_kbd.sv
segctrl.v		segctrl.v
timerint.sv		timerint.sv
vga_hw.tcl		vga_hw.tcl
wb.vh		wb.vh