BMU-Verification/
├── 📄 README.md                    # This comprehensive documentation
├── 🔧 Makefile                     # Build and simulation scripts
├── 📊 .gitignore                   # Git ignore patterns
│
├── 🧩 components/                  # Core verification components
│   ├── bmu_interface.sv            # BMU interface definition
│   ├── bmu_pkg.sv                  # UVM package declarations
│   ├── bmu_sequence_item.sv        # Transaction/sequence item
│   ├── bmu_tb.sv                   # Top-level testbench
│   ├── BMU.sv                      # BMU design wrapper
│   └── env/                        # UVM Environment Components
│       ├── bmu_agent.sv            # UVM agent for BMU interface
│       ├── bmu_driver.sv           # Driver for stimulus generation
│       ├── bmu_environment.sv      # Top-level UVM environment
│       ├── bmu_monitor.sv          # Monitor for signal observation
│       ├── bmu_scoreboard.sv       # Result checking and comparison
│       ├── bmu_sequencer.sv        # Sequence coordination
│       └── bmu_subscriber.sv       # Coverage and analysis subscriber
│
├── 🎯 dut_rm/                      # Design Under Test Reference Model
│   └── bmu_reference_model.sv      # Golden reference implementation
│
├── 🏗️ rtl/                         # RTL Design Files
│   ├── Bit_Manibulation_Unit.sv    # Main BMU RTL implementation
│   ├── bmu_design.sv               # Design wrapper
│   ├── rtl_def.sv                  # RTL definitions
│   ├── rtl_defines.sv              # RTL macros and defines
│   ├── rtl_lib.sv                  # RTL library components
│   ├── rtl_param.vh                # RTL parameters
│   └── rtl_pdef.sv                 # RTL package definitions
│
├── 🎪 sequences/                   # UVM Test Sequences
│   ├── bmu_add_sequence.sv         # Addition operation sequence
│   ├── bmu_and_sequence.sv         # Logical AND sequence
│   ├── bmu_bext_sequence.sv        # Bit extract sequence
│   ├── bmu_clz_sequence.sv         # Count leading zeros sequence
│   ├── bmu_cpop_sequence.sv        # Population count sequence
│   ├── bmu_csr_write_sequence.sv   # CSR write sequence
│   ├── bmu_errors_sequence.sv      # Error condition sequence
│   ├── bmu_gorc_sequence.sv        # Generalized OR-combine sequence
│   ├── bmu_min_sequence.sv         # Minimum operation sequence
│   ├── bmu_packu_sequence.sv       # Pack upper sequence
│   ├── bmu_reset_sequence.sv       # Reset sequence
│   ├── bmu_rol_sequence.sv         # Rotate left sequence
│   ├── bmu_sh3add_sequence.sv      # Shift-add sequence
│   ├── bmu_siext_h_sequence.sv     # Sign extend halfword sequence
│   ├── bmu_sll_sequence.sv         # Shift left logical sequence
│   ├── bmu_slt_sequence.sv         # Set less than sequence
│   ├── bmu_sra_sequence.sv         # Shift right arithmetic sequence
│   ├── bmu_valid_in_sequence.sv    # Valid input sequence
│   └── bmu_xor_sequence.sv         # Logical XOR sequence
│
└── ✅ tests/                       # UVM Test Cases
    ├── bmu_add_test.sv             # Addition operation test
    ├── bmu_and_test.sv             # Logical AND test
    ├── bmu_bext_test.sv            # Bit extract test
    ├── bmu_clz_test.sv             # Count leading zeros test
    ├── bmu_cpop_test.sv            # Population count test
    ├── bmu_csr_write_test.sv       # CSR write test
    ├── bmu_errors_test.sv          # Error condition test
    ├── bmu_gorc_test.sv            # Generalized OR-combine test
    ├── bmu_min_test.sv             # Minimum operation test
    ├── bmu_packu_test.sv           # Pack upper test
    ├── bmu_regression_test.sv      # Complete regression test
    ├── bmu_rol_test.sv             # Rotate left test
    ├── bmu_sh3add_test.sv          # Shift-add test
    ├── bmu_siext_h_test.sv         # Sign extend halfword test
    ├── bmu_sll_test.sv             # Shift left logical test
    ├── bmu_slt_test.sv             # Set less than test
    ├── bmu_sra_test.sv             # Shift right arithmetic test
    ├── bmu_valid_in_test.sv        # Valid input test
    └── bmu_xor_test.sv             # Logical XOR test