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1. hyperRAM_controller hyperRAM_controller Public

   Hyper RAM Controller for Cyclone 10 LP Eval Kit.

   Verilog 1 2

2. uwebsockets uwebsockets Public

   Forked from danni/uwebsockets

   Micropython websockets implementation

   Python

3. MicroPython_ESP32_psRAM_LoBo MicroPython_ESP32_psRAM_LoBo Public

   Forked from loboris/MicroPython_ESP32_psRAM_LoBo

   MicroPython for ESP32 with psRAM support

   C

4. cgpt_info cgpt_info Public

5. OpenHBMC OpenHBMC Public

   Forked from OVGN/OpenHBMC

   Open-source high performance AXI4-based HyperRAM memory controller forked for Altera FPGA

   Verilog

6. HyperBUS HyperBUS Public

   Forked from gtjennings1/HyperBUS

   port design to Cyclone 10 LP

   Verilog