This repository contains the implementation and verification environment for a parameterizable synchronous FIFO (First-In-First-Out) buffer in SystemVerilog. The design supports key FIFO operations along with status flags and includes a comprehensive UVM-based testbench and verification infrastructure.
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Configurable FIFO depth and data width
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Asynchronous reset with proper initialization of memory and control signals
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Write (wr_en) and read (rd_en) operations with simultaneous read/write handling
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Status flags:
full,almost_fullempty,almost_emptyoverflow,underflowwr_ackacknowledgement for successful writes
├── design/ # RTL source for FIFO and related modules
├── tb/ # Top-level testbench instantiation
├── pkg/
│ ├── coverage_pkg/ # Coverage definitions and configurations
│ ├── transaction_pkg/ # Sequence item and transaction definitions
│ ├── monitor_pkg/ # Monitors for interface and protocol checking
│ └── scoreboard_pkg/ # Scoreboard and reference model integration
├── interface/ # UVM interfaces and virtual interface definitions
├── shared_pkg/ # Shared types, parameters, and utilities
├── sim/ # Simulation scripts, run files, transcripts, waveforms
└── reports/
└── coverage_report/ # Generated coverage reports
The functional verification plan defines the following directed and random scenarios to validate FIFO behavior, along with corresponding coverage goals and reference model checks:
| Label | Design Requirement | Stimulus | Coverage & Checks |
|---|---|---|---|
| FIFO_1 | Reset clears FIFO and all flags are reset correctly | Directed reset, then random reset deassertion | Immediate assertions on clear and flags reset |
| FIFO_2 | Write stores data and updates full/ almost_full flags | Randomize wr_en and data_in (no read) |
Cover all data_in values and flag updatesConcurrent assertions against reference model |
| FIFO_3 | Read outputs data and updates empty/ almost_empty flags | Randomize rd_en (no write) |
Cover flag transitions during reads Scoreboard-based data checking |
| FIFO_4 | Only one operation occurs when both wr_en and rd_en are high |
Randomize both wr_en and rd_en |
Cover simultaneous read/write cases Reference model asserts correct behavior |
| FIFO_5 | Ignore writes when full; assert overflow on invalid write |
Randomize wr_en when FIFO is full |
Cover full flag transitions and overflow events Immediate overflow detection assertions |
| FIFO_6 | Ignore reads when empty; assert underflow on invalid read |
Randomize rd_en when FIFO is empty |
Cover empty flag transitions and underflow events Immediate underflow detection assertions |
| FIFO_7 | Assert wr_ack on valid writes |
Randomize wr_en when FIFO not full |
Cover write acknowledgments Concurrent assertions for wr_ack |
| FIFO_8 | Handle boundary transitions (e.g., full→almost_full, empty→almost_empty) | Push FIFO to boundary through reads/writes | Cover boundary condition transitions Concurrent assertions for correct flag handling |
Detailed plan and expected coverage goals are outlined in the Verification Plan document. fileciteturn1file1
During design reviews and verification runs, the following modifications were applied to enhance correctness and robustness:
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Initialization of Memory Array
- Added explicit initialization of the internal memory (
mem) to all zeros on reset. fileciteturn1file2
- Added explicit initialization of the internal memory (
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Write Acknowledgement (
wr_ack)- Ensured
wr_ackis initialized to0on reset and asserted only on successful write transactions. fileciteturn1file2
- Ensured
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Underflow Handling
- Moved
underflowflag assignment into a sequential block under the read logic to avoid combinational hazards. fileciteturn1file2
- Moved
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Count Management for Simultaneous Read/Write
- Added explicit cases to increment/decrement
countappropriately when both read and write are asserted. fileciteturn1file2
- Added explicit cases to increment/decrement
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Almost Full / Almost Empty Signals
- Corrected thresholds:
almost_fullnow triggers atFIFO_DEPTH - 1;almost_emptyatcount == 1. fileciteturn1file2
- Corrected thresholds:
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Requirements
- SystemVerilog-capable simulator (e.g., VCS, Xcelium, or QuestaSim)
- UVM library installed and accessible in your simulation environment
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Running Simulations
cd sim ./run_fifo_uvm.sh # Executes all UVM tests and generates reports
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Viewing Results
- Waveforms: Available in
sim/waves/ - Transcript Logs: Available in
sim/logs/ - Coverage Reports: HTML reports in
reports/coverage_report/
- Waveforms: Available in
Contributions are welcome! Please fork the repository and submit pull requests for bug fixes, feature enhancements, or improved coverage scenarios.