GitHub - sulfog/digital-design: VHDL Code Dump for Digital Circuits Lab (EE214), Spring 2017

Name		Name	Last commit message	Last commit date
Latest commit History 27 Commits
EE214 - Experiment 1		EE214 - Experiment 1
EE214 - Experiment 2		EE214 - Experiment 2
EE214 - Experiment 3		EE214 - Experiment 3
EE214 - Experiment 4		EE214 - Experiment 4
EE214 - Experiment 5		EE214 - Experiment 5
EE214 - Experiment 6-7		EE214 - Experiment 6-7
EE214 - Experiment 8		EE214 - Experiment 8
EE214 - Midsem		EE214 - Midsem
EE214 - VHDL Tutorial		EE214 - VHDL Tutorial
Generic Testbench		Generic Testbench
Quartus Projects		Quartus Projects
Scan Chain Guide		Scan Chain Guide
Submissions		Submissions
.gitignore		.gitignore
AFG User Manual.pdf		AFG User Manual.pdf
Behavioural FSM.tgz		Behavioural FSM.tgz
Behavioural GCD.tgz		Behavioural GCD.tgz
Behavioural Shift-Add Multiplier.tgz		Behavioural Shift-Add Multiplier.tgz
EE214 Laboratory Manual.pdf		EE214 Laboratory Manual.pdf
Getting Started with Altera, ModelSim.pdf		Getting Started with Altera, ModelSim.pdf
JTAG Instructions.txt		JTAG Instructions.txt
modelsim-installation.md		modelsim-installation.md
submission_template.tgz		submission_template.tgz