Time over android debuging bridge

DIG-SYSTEM: A high-performance VHDL DPLL for Xilinx FPGAs. Implements IDELAYE2 primitives with sigma-delta dithering for sub-tap resolution. Features adaptive damping, phase velocity tracking, and robust hysteresis locking. Optimized for precision clock and data alignment.

A lightweight, background daemon for macOS that fixes the `00:00` clock issue on Ajazz wireless mouse dock screens (e.g., AJ179 Apex, AJ199, AJ159).

Deterministic time-governance engine for the Gold Cluster. Enforces the Entropy Ban on temporal data through quantized clock-syncing and monotonic pulse-width validation for the RP2040 substrate.