Single clock simple dual-port RAM wrapper.
| No. | File name | Description |
|---|---|---|
| 1 | README.md | Module Specification |
| 2 | FIREEEE_RAM.v | Module |
| 3 | FIREEEE_RAM_tb.sv | Testbench |
| 4 | Sim | Simulation Scripts |
| Item | Status |
|---|---|
| Version | 0.01 |
| Date | 2026/03/10 |
| Verified | Yes |
| Real Machine Checked | No |
- RTL simulation
- Code coverage
Some inputs may not take effect depending on the RAM used in combination with this module.
| Port name | Description | Synchronous / Asynchronous | Clock Domain | Active low |
|---|---|---|---|---|
| CLK_I | Clock | - | - | No |
| WEN_I | Write Enable | Synchronous | CLK_I | No |
| WADDR_I | Write Address | Synchronous | CLK_I | No |
| WDATA_I | Write Data | Synchronous | CLK_I | No |
| REN_I | Read Enable | Synchronous | CLK_I | No |
| RADDR_I | Read Address | Synchronous | CLK_I | No |
| Port name | Description | Synchronous / Asynchronous | Clock Domain | Active low |
|---|---|---|---|---|
| RDATA_O | Read Data | Synchronous | CLK_I | No |
Some parameters may not take effect depending on the RAM used in combination with this module.
| Parameter name | Description | Default Value |
|---|---|---|
| DATA_WIDTH | Data Bit Width | 32 |
| ADDR_WIDTH | Address Width | 8 |
| OUT_REG_EN | Output Register Enable | 1'b0 (Disable) |
| RAM_INIT_FILE | RAM Initialization File Name (Optional) | "" (None) |
No timing chart in this module. Please see FIREEEE_DATA_RAM for actual operation.
- Some inputs and parametes may not take effect depending on the RAM used in combination with this module.
- You have to your own single clock simple dual-port RAM by define macro.
Initial Release of the Specification.
- Add module & related files. (2026/03/10)
- Add simulation & verification results. (2026/03/10)