š„FIREEEE (FIR filter as Easily, Expandable, Enhanceable and Embedded) is the open-source Verilog module for implementing serial FIR filters to the FPGA.š„
š„FIREEEEš„ is a configurable serial FIR filter implementation written in Verilog and a successor to the FIR_x2 project.
The goal of this project is to provide a portable FIR filter architecture capable of supporting very long tap counts while remaining compatible with a wide range of FPGA toolchains.
Note: The project is currently under active development. The specification and the Verilog modules are being developed in parallel.
- Configurable serial FIR filter architecture
- Designed for FPGA implementations
- Supports very long tap counts
- Vendor-independent design where possible
This is under construction.
This is under construction.
A serial FIR filter (also known as a single-MAC FIR filter) is an architecture that performs multiply-accumulate operations sequentially using a single multiplier and adder per channel.
This approach reduces hardware resource usage and is suitable for FPGA designs where arithmetic resources are limited.
Many FIR filter implementations on GitHub use fully parallel multipliers and adders. While this allows high throughput, the number of taps is limited by hardware resources.
Vendor-generated FIR IP cores often use serial architectures, but they are typically vendor-specific and lack portability.
This project aims to provide a portable FIR filter architecture capable of supporting very long tap counts.
3. Why was the license changed from CERN-OHL-W v2 to CERN-OHL-P v2 (on FIR_x2)?
The main reason is usability.
š„FIREEEEš„ aims to support both inferred and vendor-specific RAM/ROM implementations. Using CERN-OHL-W v2 would require modified design sources to be released under the same license when the design is redistributed.
To allow more flexible integration with different FPGA toolchains, this project adopts the more permissive CERN-OHL-P v2.
Yes, contributions are welcome!
If you would like to improve any part of this repository, including the specification, please fork the repository and submit a pull request.
Questions and bug reports are also welcome. You can start by posting in the Q&A section under Discussions.
Copyright AUDIY 2026.
This source describes Open Hardware and is licensed under the CERN-OHL-P v2.
You may redistribute and modify this source and make products using it under the terms of the CERN-OHL-P v2 (https:/cern.ch/cern-ohl).
This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-P v2 for applicable conditions.