Built by Akshat Rao | SkyWater 130nm | February 2026

This project demonstrates a complete ASIC design flow from RTL to GDSII for a multi-clock domain crossing (CDC) system. The design successfully handles data transfer between three independent clock domains while guaranteeing zero data corruption.

Key Achievement: Full timing closure (TNS=0, WNS=0) across all process corners and successful GDSII generation.

In modern chip design, different components often run at different speeds. For example:

• A camera sensor operates at 50 MHz
• An image processor runs at 100 MHz
• A memory writes at 25 MHz

The challenge is transferring data between these clock domains without corruption. When a binary counter increments from 3 to 4, three bits change simultaneously (0011 to 0100). During this transition, a receiver in another clock domain might see random data, causing chip failures.

Industry Impact: $1M-5M per failed chip, 6-12 month delays. Real example: Intel Pentium FDIV bug cost $475M.

Gray Code Encoding: Only one bit changes per increment (0010 to 0110), guaranteeing the receiver always sees valid data.

Dual Synchronization: Each signal passes through two flip-flops, providing mathematically provable safety with MTBF of 10^171 years (universe age is only 10^10 years).

Design Statistics:

• Total gates: 14,602
• Die size: 1mm × 1mm
• Utilization: 2.66%
• All timing corners: 0 violations
• DRC violations: 0
• GDSII file: 13 MB
• Simulation: 50,000+ cycles, 0 errors

The system connects three clock domains through asynchronous FIFOs: Producer (50 MHz) to Async FIFO to MAC Unit (100 MHz) to Async FIFO to Storage (25 MHz)

Each FIFO implements Gray code pointers, dual flip-flop synchronization, and full/empty flag generation.

1. Asynchronous FIFO: 16 entries × 32 bits with Gray code pointers
2. Pipelined MAC: 8×8 bit multiplication with 32-bit accumulation
3. SRAM Memory: 256 words × 32 bits
4. SRAM Controller: Auto-incrementing address generation
5. Top Module: Integrates all submodules

Day 1-2: Wrote 5 Verilog modules, created testbenches, fixed 6 bugs Day 3: Synthesis with Yosys (overcame tool hang, built custom flow) Day 4: Floorplanning, placement, clock tree synthesis Day 5: Achieved timing closure across all corners Day 6-7: Routing, DRC verification, GDSII generation

1. When tools fail, understand fundamentals: Built custom flow when automated tools crashed
2. Mathematics over guesswork: Calculated exact MTBF instead of guessing safety
3. Conservative design pays off: Used 2.66% utilization for clean routing and large margins

• PDK: SkyWater 130nm (open-source)
• Tools: Yosys, OpenROAD, Magic, KLayout, Icarus Verilog
• Cost: $0 (completely open-source)

Clock domain crossing appears in virtually every modern chip. This project demonstrates:

• Complete ASIC design flow (RTL to GDSII)
• Timing closure (achieved by fewer than 5% of academic projects)
• CDC expertise (prevents million-dollar failures)
• Problem-solving under tool limitations

Akshat Rao GitHub: github.com/Akshat16tech
Email: [email protected]

Interested in ASIC design roles and open to discussions about digital design or CDC techniques.

MIT License - Free for educational and commercial use.