I am a Fullstack Web Developer and Systems Engineer with a knack for identifying bottlenecks and building custom tooling to solve them. I don't just use libraries; I dive into kernel-level observability, Android internals, and financial middleware.

• My Philosophy: "Do not cry over spilt milk." I believe in rapid iteration, fixing what breaks, and moving forward.
• Offline: When I'm not coding, I'm deep-diving into technical analysis videos, scientific documentaries, and deconstructing film theory.

The Problem: Kubernetes/Docker cluster monitoring is opaque and SaaS costs are hidden until the bill arrives. The Solution: A high-performance analyzer written in Rust and Go.

• Tech: Rust (eBPF), Go, Kubernetes, Docker.
• Key Capabilities: Deep packet inspection on any network interface, real-time error analysis, and precise cost estimation for cloud clusters (AWS/GCP/Azure).
• Deployment: Fully self-hostable to avoid SaaS vendor lock-in.

The Problem: Android's Scoped Storage (SAF) and Phantom Process Killer make serious development on mobile impossible with legacy apps like Termux. The Solution: A modern terminal built with a Rust PTY core and Kotlin Jetpack Compose UI.

• Tech: Rust (Core), Kotlin (UI), JNI Bridge.
• Architecture:
  • SAF-VFS Bridge: Virtual filesystem mapping SAF URIs to Unix paths (Bypassing storage restrictions).
  • Hybrid UI: Combines a native GUI file explorer/editor with a raw terminal.
  • Stability: Engineered to resist Android's background process killing.

The Solution: A high-frequency bridge connecting legacy trading platforms (MetaTrader 5) with modern Fintech APIs (Dhan).

• Tech: Python, Websockets, REST APIs.
• Function: Handles real-time order placement and syncing. Uses efficient polling and Websockets to execute trades triggered by custom EAs (Expert Advisors) or manual MT5 inputs instantly on the exchange.

The Solution: A Python-based Blender Addon streamlining the 3D rigging workflow.

• Function: Automates the tedious import of rigging models (.blend), manages version control within the viewport, and auto-fixes override linking issues.

The Challenge: Designing efficient hardware for memory-to-memory data transfer without burdening the CPU. The Solution: A fully verified 2-Channel DMA Controller implemented at the Register Transfer Level (RTL).

• Tech: SystemVerilog, UVM (Universal Verification Methodology), Verilog.
• Engineering:
  • RTL Design: Implemented complex state machines and data paths in SystemVerilog.
  • Verification: Built a complete UVM Testbench environment to validate functionality, edge cases, and ensure 100% code coverage.

Hardware / Silicon	Systems & Core	Web Fullstack	Mobile & Creative	DevOps & Cloud