Verilog_HDL

This is my Verilog repository which contains some Verilog tutorials.

Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
ALU_16bit		ALU_16bit
ALU_Hierarchical		ALU_Hierarchical
Automatic_Garage_Door_Controller		Automatic_Garage_Door_Controller
Cyclic_Redundancy_Check		Cyclic_Redundancy_Check
Integer_Clock_Divider		Integer_Clock_Divider
Linear_Feedback_Shift_Register		Linear_Feedback_Shift_Register
Mealy_1101_detector		Mealy_1101_detector
Moore_1101_detector		Moore_1101_detector
Register_file8x16		Register_file8x16
Universal_Asynchronous_Receiver_Transmitter_TX		Universal_Asynchronous_Receiver_Transmitter_TX
Up_Down_counter		Up_Down_counter
README.md		README.md

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